TNETV2664FIBZWT datasheet(113/249 Pages) TI1

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TMS320C6424

www.ti.com

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

Table 3-40. EMIFA Block Major Configuration Choices

MAJOR

PINMUX SELECTION FIELDS

RESULTING PERIPHERALS/PINS

CONFIG.

PCIEN

AEM

RMII

CS3SEL

CS4SEL

CS5SEL

PCI

(1)

EMIFA

(2)

RMII

GPIO

OPTION

58 GP Pins:

000

GP[96:89], GP[54:5]

RMII:

50 GP Pins:

RMRXER, RMRXD[1:0],

000

GP[96:89], GP[54:53],

RMTXD[1:0], REFCLK,

GP[51:34], GP[26:5],

RMCRSDV, RMTXEN

16-bit EMIFA (Async) Pinout

Mode 2:

EM_A[21:0], EM_D[15:0],

13 GP pins:

EM_R/W, EM_CS2,

GP[54:52], GP[31:22]

EM_BA[1:0],

EM_WAIT/(RDY/BSY),

Optional Selection:

010

0 or 1

EM_WE, EM_OE

GP[33] (CS5SEL = 0),

GP[32] (CS4SEL = 0),

Optional Selection:

GP[13] (CS3SEL = 0)

EM_CS5 (CS5SEL = 1),

EM_CS4 (CS4SEL = 1),

EM_CS3 (CS3SEL = 1)

16-bit EMIFA (Async) Pinout

Mode 2:

EM_A[21:0], EM_D[15:0],

7 GP pins:

RMII:

EM_R/W, EM_CS2,

GP[54:53], GP[26:22]

RMRXER, RMRXD[1:0],

EM_BA[1:0],

010

0 or 1

RMTXD[1:0], REFCLK,

EM_WAIT/(RDY/BSY),

Optional Selection:

RMCRSDV, RMTXEN

EM_WE, EM_OE

GP[13] (CS3SEL = 0)

Optional Selection:

EM_CS3 (CS3SEL = 1)

8-bit EMIFA (NAND) Pinout

Mode 5:

44 GP pins:

EM_D[7:0], EM_A[2:1],

GP[96:89], GP[54:34],

EM_CS2,

GP[31:22], GP[11:10],

EM_WAIT/(RDY/BSY),

GP[7:5]

101

0 or 1

EM_WE, EM_OE

Optional Selection:

GP[33] (CS5SEL = 0),

EM_CS5 (CS5SEL = 1),

GP[32] (CS4SEL = 0),

EM_CS4 (CS4SEL = 1),

GP[13] (CS3SEL = 0)

EM_CS3 (CS3SEL = 1)

8-bit EMIFA (NAND) Pinout

Mode 5:

38 GP pins:

EM_D[7:0], EM_A[2:1],

GP[96:89], GP[54:34],

RMII:

EM_CS2,

GP[26:22], GP[11:10],

RMRXER, RMRXD[1:0],

101

0 or 1

EM_WAIT/(RDY/BSY),

GP[7:5]

RMTXD[1:0], REFCLK,

EM_WE, EM_OE

RMCRSDV, RMTXEN

Optional Selection:

GP[13] (CS3SEL = 0)

EM_CS3 (CS3SEL = 1)

(1)

PCI pins span across multiple Pin Mux Blocks ( Section 3.7.3.2 , Peripherals Spanning Multiple Pin Mux Blocks). This table only refers to the PCI pins in the EMIFA Block.

(2)

The EMIFA pins EM_WAIT/(RDY/BSY), EM_OE, and EM_WE are non-multiplexed pins. They are available in all the configuration options. However, they are only useful if additional

EMIFA pins are functional. Therefore in this table, these pins are only listed in configuration options C,D,E,F,J, and K.

Device Configurations

113

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