TNETV6446AINZWT datasheet(119/227 Pages) TI1

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TMS320DM6446

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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

6.9

Enhanced Direct Memory Access (EDMA3) Controller

The EDMA3 controller handles all data transfers between memories and the device slave peripherals on

the DM6446 device. These data transfers include cache servicing, non-cacheable memory accesses,

user-programmed data transfers, and host accesses. These are summarized as follows:

•

Transfer to/from on-chip memories

–

Coprocessor shared memory

–

DSP L1D memory

–

DSP L2 memory

–

ARM program/data RAM

•

Transfer to/from external storage

–

DDR2 SDRAM

–

NAND flash

–

Asynchronous EMIF

–

Smart Media, SD, MMC, xD media storage

–

ATA/CF

•

Transfer to/from peripherals/hosts

–

VLYNQ

–

ASP

–

SPI

–

PWM

–

UART

The EDMA3 controller supports two addressing modes: constant addressing mode and increment

addressing mode. On the DM6446 device, constant addressing mode is not supported by any peripheral

or internal memory. For more information on these two addressing modes, see the TMS320DM644x

DMSoC Enhanced Direct Memory Access (EDMA3) Controller User's Guide (literature number

SPRUE23).

6.9.1

EDMA3 Channel Synchronization Events

The EDMA3 supports up to 64 EDMA3 channels which service peripheral devices and external memory.

Table 6-29 lists the source of EDMA3 synchronization events associated with each of the programmable

EDMA3 channels. For the DM6446 device, the association of an event to a channel is fixed; each of the

EDMA3 channels has one specific event associated with it. These specific events are captured in the

EDMA3 event registers (ER, ERH) even if the events are disabled by the EDMA3 event enable registers

(EER, EERH). For more detailed information on the EDMA3 module and how EDMA3 events are enabled,

captured, processed, linked, chained, and cleared, etc., see the TMS320DM644x DMSoC Enhanced

Direct Memory Access (EDMA3) Controller User's Guide (literature number SPRUE23).

Table 6-29. DM6446 EDMA3 Channel Synchronization Events(1)

EDMA3

EVENT NAME

EVENT DESCRIPTION

CHANNEL

0-1

Reserved

XEVT

ASP Transmit Event

REVT

ASP Receive Event

HISTEVT

VPSS Histogram Event

H3AEVT

VPSS H3A Event

PRVUEVT

VPSS Previewer Event

RSZEVT

VPSS Resizer Event

(1)

In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate

transfer completion events. For more detailed information on EDMA3 event-transfer chaining, see the TMS320DM644x DMSoC

Enhanced Direct Memory Access (EDMA3) Controller User's Guide (literature number SPRUE23).

Peripheral and Electrical Specifications

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