TNETV2685FIBZUT9 datasheet(139/191 Pages) TI1

139 / 191 page

TMS320DM647

TMS320DM648

www.ti.com

SPRS372H – MAY 2007 – REVISED APRIL 2012

6.16.3 HPI Electrical Data/Timing

Table 6-66. Timing Requirements for Host-Port Interface Cycles(1) (2) (see Figure 6-40 through Figure 6-

47)

720, 800, 900, 1100

NO.

UNIT

MIN

MAX

tsu(HASL-HSTBL)

Setup time, HAS low before HSTROBE low

th(HSTBL-HASL)

Hold time, HAS low after HSTROBE low

tsu(SELV-HASL)

Setup time, select signals(3) valid before HAS low

th(HASL-SELV)

Hold time, select signals(3) valid after HAS low

tw(HSTBL)

Pulse duration, HSTROBE low

tw(HSTBH)

Pulse duration, HSTROBE high between consecutive accesses

tsu(SELV-HSTBL)

Setup time, select signals(3) valid before HSTROBE low

th(HSTBL-SELV)

Hold time, select signals(3) valid after HSTROBE low

tsu(HDV-HSTBH)

Setup time, host data valid before HSTROBE high

th(HSTBH-HDV)

Hold time, host data valid after HSTROBE high

tsu(HCSL-HSTBL)

Setup time, HCS low before HSTROBE low

Hold time, HSTROBE low after HRDY low. HSTROBE should not be

th(HRDYL-HSTBL)

inactivated until HRDY is active (low); otherwise, HPI writes will not

1.1

complete properly.

(1)

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT (HDS1 XOR HDS2)] OR HCS.

(2)

M = SYSCLK3 period = 6/CPU clock frequency in ns.

(3)

Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.

Peripheral Information and Electrical Specifications

139

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