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GD25Q128CXIGX Datasheet(PDF) 18 Page - ELM Electronics

No. de pieza GD25Q128CXIGX
Descripción Electrónicos  3.3V Uniform Sector Dual and Quad Serial Flash
PDF  69 Pages
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Fabricante Electrónico  ELM [ELM Electronics]
Página de inicio  http://www.elmelectronics.com
Logo ELM - ELM Electronics

GD25Q128CXIGX Datasheet(HTML) 18 Page - ELM Electronics

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Rev.1.2
69 -
http://www.elm-tech.com
GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
7.1. Write Enable (WREN)(06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch
(WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE),
Write Status Register (WRSR) and Erase/Program Security Register command. The Write Enable (WREN)
command sequence: CS# goes low → sending the Write Enable command → CS# goes high.
Command
0 1 2 3 4 5 6 7
06H
CS#
SCLK
SI
SO
High-Z
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command
sequence: CS# goes low → Sending the Write Disable command → CS# goes high. The WEL bit is reset by
following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,
Block Erase, Chip Erase, Erase/Program Security Register and Reset commands.
Command
0 1 2 3 4 5 6 7
04H
CS#
SCLK
SI
SO
High-Z
Figure 3. Write Enable Sequence Diagram
Figure 4. Write Disable Sequence Diagram
CS#
SCLK
IO0
IO1
IO2
IO3
0 1
Command
06H
Figure 3a. Write Enable Sequence Diagram (QPI)


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