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GD25Q128CXIGX Datasheet(PDF) 35 Page - ELM Electronics |
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GD25Q128CXIGX Datasheet(HTML) 35 Page - ELM Electronics |
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35 / 69 page  35 Rev.1.2 69 - http://www.elm-tech.com GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash 7.18. 64KB Block Erase (BE) (D8H) The 64KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 64KB Block Erase command sequence: CS# goes low → sending 64KB Block Erase command → 3-byte address on SI → CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1 and BP0) bits is not executed. Figure 20. 64KB Block Erase Sequence Diagram Command 0 1 2 3 4 5 6 7 D8H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0 24 Bits Address 23 22 Figure 20a. 64KB Block Erase Sequence Diagram (QPI) CS# SCLK IO0 IO1 IO2 IO3 0 1 2 3 4 5 Command D8H 6 7 A23-16 A15-8 A7-0 20 16 12 8 4 0 13 9 5 1 14 10 6 2 15 11 7 3 23 19 22 18 21 17 |
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