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GD25Q128CXIGX Datasheet(PDF) 36 Page - ELM Electronics |
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GD25Q128CXIGX Datasheet(HTML) 36 Page - ELM Electronics |
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36 / 69 page  36 Rev.1.2 69 - http://www.elm-tech.com GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash 7.19. Chip Erase (CE) (60/C7H) The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Chip Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence. The Chip Erase command sequence: CS# goes low → sending Chip Erase command → CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self- timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed only if all Block Protect (BP2, BP1 and BP0) bits are 0. The Chip Erase (CE) command is ignored if one or more sectors are protected. Figure 21. Chip Erase Sequence Diagram Command 0 1 2 3 4 5 6 7 60H or C7H CS# SCLK SI Figure 21a. Chip Erase Sequence Diagram (QPI) CS# SCLK IO0 IO1 IO2 IO3 0 1 Command C7H/60H |
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