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GD25Q128CXIGX Datasheet(PDF) 12 Page - ELM Electronics |
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GD25Q128CXIGX Datasheet(HTML) 12 Page - ELM Electronics |
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12 / 69 page  12 Rev.1.2 69 - http://www.elm-tech.com GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash QE bit. The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD#/RESET# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD#/RESET# pins are tied directly to the power supply or ground). LB3, LB2, LB1 bits. The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time Programmable, once its set to 1, the Security Registers will become read-only permanently. CMP bit. The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4- BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0. SUS1, SUS2 bits. The SUS1 and SUS2 bits are read only bit in the status register (S15 and S10) that are set to 1 after executing an Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1, and the Program Suspend will set the SUS2 to 1) . The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command as well as a power-down, power-up cycle. WPS bit. The WPS Bit is used to select which Write Protect scheme should be used. When WPS=0, the device will use the combination of CMP, BP (4:0) bits to protect a specific area of the memory array. When WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The default value for all Individual Block Lock bits is 1 upon device power on or after reset. DRV1/DRV0. The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations. DRV1, DRV0 Driver Strength 00 100% 01 75% 10 50% (default) 11 25% HOLD/RST The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware pin for 8-pin packages. When HOLD/RST=0, the pin acts as HOLD#, When the HOLD/RST=1, the pin acts as RESET#. However, the HOLD# or RESET# function are only available when QE=0, If QE=1, The HOLD# and RESET# functions are disabled, the pin acts as dedicated data I/O pin. |
Número de pieza similar - GD25Q128CXIGX |
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Descripción similar - GD25Q128CXIGX |
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