### Electronic Components of PS-RPC (Power Supply - Resistive Plate Chamber) A **Resistive Plate Chamber (RPC)** is a particle detector that uses a high-voltage gas gap to detect ionizing particles. The "PS-RPC" generally refers to the **Power Supply** and the associated **Readout Electronics** required to operate these chambers. --- ### 1. High Voltage (HV) Power Supply System The most critical electronic component for an RPC is the high-voltage system, as the chamber operates in either "Avalanche" or "Streamer" mode, requiring high electric fields. | Component | Function | Typical Specifications | | :--- | :--- | :--- | | **HV Generator** | Provides the primary DC potential to the resistive plates. | 9 kV to 12 kV (Gas dependent) | | **Voltage Divider** | Distributes voltage equally across multiple gaps in multi-gap RPCs (MRPCs). | High-precision resistor chain | | **Current Monitor** | Monitors "Dark Current" to detect gas contamination or aging. | Nano-ampere (nA) sensitivity | | **Filtering Circuit** | Removes AC ripples and noise from the HV line to prevent false triggers. | RC Low-pass filters | --- ### 2. Front-End Electronics (FEE) The FEE is responsible for processing the very small induced charges (pico-Coulombs) from the pick-up electrodes. * **Preamplifier:** Boosts the weak signal induced by the electron avalanche. * **Discriminator:** Converts the analog signal into a digital pulse (LVDS or TTL) if it exceeds a set threshold. * **Time-to-Digital Converter (TDC):** Measures the exact time the particle hit the detector with picosecond resolution. --- ### 3. Data Acquisition (DAQ) and Control These components manage the flow of information from the detector to the storage servers. 1. **FPGA (Field Programmable Gate Array):** Acts as the "brain," handling trigger logic, data compression, and communication. 2. **LV Power Supply:** Provides low voltage (typically 1.2V to 5V) to the FEE and FPGAs. 3. **Communication Interface:** Usually Gigabit Ethernet or Optical Fibers to transfer high volumes of event data. --- ### 4. Basic Signal Path Code Example In modern digital RPC systems, the signal is often processed via a simple logic gate or FPGA trigger. Below is a conceptual representation of a trigger logic in Verilog: ```verilog module rpc_trigger_logic ( input wire clk, input wire [7:0] strip_signals, // Signals from 8 RPC strips output reg trigger_out ); always @(posedge clk) begin // If any strip detects a particle above threshold if (strip_signals != 8'b00000000) begin trigger_out <= 1'b1; end else begin trigger_out <= 1'b0; end end endmodule ``` --- ### Summary of Operating Modes | Feature | Avalanche Mode | Streamer Mode | | :--- | :--- | :--- | | **HV Level** | Lower | Higher | | **Charge Produced** | Small (~pC) | Large (~nC) | | **Electronic Complexity** | High (Needs high-gain amps) | Low (Simple discriminators) | | **Rate Capability** | High | Low |