Description
The TC518128A is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518128A utilizes
a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power storage. The
TC518128A operates from a single 5V power supply. Refreshing is supported by a refresh (RFSH) input which enables two types of
refreshing-auto refresh and self refresh. The TC518128A features a static RAM-like interface with a write cycle in which the input
data is written into the memory cell at the rising edge of R/W thus simplifying the microprocessor interface.
The TC518128A is pin-compatible with the 1M bit CMOS static RAM JEDEC standard and is available in a 32-pin, 0.6 inch and
0.3 inch width plastic DIP, a small outline plastic flat package, and a 32-pin thin small outline plastic package (forward type).

Features
• Organization: 131,072 words x 8 bits
• Single 5V power supply
• Fast access time
*CEA CE Access Time
OE Access Time
TOEA
TRC Cycle Time
Power Dissipation
Self Refresh Current
TC518128A Family
-80
-10
80ns
100ns
35ns
40ns
130ns
160ns
385mW 330mW
1mA/200µA (L version)
Auto refresh is supported by an internal refresh address
counter
Self refresh is supported by an internal timer
Inputs and outputs TTL compatible
• Refresh: 512 refrosh cycles/8ms
Auto refresh power down feature
Pin compatible: 1M SRAM (JEDEC)
Package
-
- TC518128AP/APL
TC518128AF/AFL
- TC518128ASP/ASPL
TC518128AFW/AFWL:
- TC518128AFTL
-12
120ns
50ns
190ns
275mW
: DIP32-P-600
: SOP32-P-450
: DIP32-P-300
SOP32-P-525
: TSOP32-P-0820