1 Features
• Ultra-low jitter BAW VCO based Ethernet clocks
– 13fs typical RMS jitter at 625MHz with 4MHz 1st
order high-pass filter (HPF)
– 24fs typical RMS jitter at 312.5MHz with 4MHz
1st order HPF
– 42fs typical/ 60fs maximum RMS jitter at
312.5MHz
– 47fs typical/ 65fs maximum RMS jitter at
156.25MHz
• 1 high-performance Digital Phase Locked Loop
(DPLL) with 2 Analog Phase Locked Loops
(APLLs)
– Programmable DPLL loop filter bandwidth from
1mHz to 4kHz
– < 1ppt DCO frequency adjustment step size
• 2 differential or single-ended DPLL inputs
– 1Hz (1PPS) to 800MHz input frequency
– Digital Holdover and Hitless Switching
• 12 differential outputs with programmable HSDS,
AC-LVPECL, LVDS and HSCL formats
– Up to 16 total frequency outputs when
configured with 6 LVCMOS frequency outputs
on OUT0_P/N, OUT1_P/N, GPIO1 and GPIO2
and 10 differential outputs on OUT2_P/N to
OUT11_P/N
– 1Hz (1PPS) to 1250MHz output frequency with
programmable swing and common mode
– PCIe Gen 1 to 6 compliant
• I2C or 3-wire/4-wire SPI

2 Applications
• Wired networking
– Inter/Intra DC interconnect
– Timing card, line card, fixed card (pizza box)
• SyncE (G.8262), SONET/SDH (Stratum 3/3E,
G.813, GR-1244, GR-253), IEEE-1588 PTP
secondary clock
• Jitter cleaning, wander attenuation, and reference
clock generation for 112G/224G PAM-4 SerDes
• 100G-800G data center switches, core routers,
edge routers, WLAN
• Data center and enterprise computing
– Smart Network Interface Card (NIC)
• Optical Transport Networks (OTN G.709)
• Broadband fixed line access
• Industrial
– Test and measurement
– Medical imaging

3 Description
The LMK5B12212 is a high-performance network
synchronizer and jitter cleaner designed to meet the
stringent requirements of ethernet-based networking
applications with < 5ns timing accuracy (class D).
The network synchronizer integrates a DPLL to
provide hitless switching and jitter attenuation with
programmable loop bandwidth (LBW) and no external
loop filters, maximizing flexibility and ease of use. The
DPLL phase locks an integrated APLL to the provided
reference input.
APLL1 features an ultra high performance PLL
with TI's proprietary Bulk Acoustic Wave (BAW)
technology (known as the BAW APLL) and can
generate 312.5MHz output clocks with 42fs typical /
60fs maximum RMS jitter irrespective of the DPLL
reference input frequency and jitter characteristics.
APLL2 provides for a second frequency and/or
synchronization domain.
Reference validation circuitry monitors the DPLL
reference clocks and performs a hitless switch
between inputs upon detecting a switchover event.
Zero-Delay Mode (ZDM) and phase cancellation can
be enabled to control the phase relationship from
input to outputs.
The device is fully programmable through I2C or SPI.
The integrated EEPROM can be used to customize
system start-up clocks. The device also features
factory default ROM profiles as fallback options.