Features
• Synchronous Programmable ÷N Counter N = 3 to 9999
or 15999
• Presettable Down-Counter
• Fully Static Operation
• Mode-Select Control of Initial Decade Counting
Function (÷10, 8, 5, 4, 2)
• Master Preset Initialization
• Latchable ÷N Output
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V

Applications
• Communications Digital Frequency Synthesizers;
VHF, UHF, FM, AM, etc.
• Fixed or Programmable Frequency Division
• “Time Out” Timer for Consumer-Application Industrial
Controls

Description
The ’HC4059 are high-speed silicon-gate devices that are
pin-compatible with the CD4059A devices of the CD4000B
series. These devices are divide-by-N down-counters that
can be programmed to divide an input frequency by any
number “N” from 3 to 15,999. The output signal is a pulse
one clock cycle wide occurring at a rate equal to the input
frequency divide by N. The down-counter is preset by means
of 16 jam inputs.
The three Mode-Select Inputs Ka, Kb and Kc determine the
modulus (“divide-by” number) of the first and last counting
sections in accordance with the truth table. Every time the first
(fastest) counting section goes through one cycle, it reduces by
1 the number that has been preset (jammed) into the three
decades of the intermediate counting section an the last
counting section, which consists of flip-flops that are not
needed for opening the first counting section. For example, in
the ÷2 mode, only one flip-flop is needed in the first counting
section. Therefore the last counting section has three flip-flops
that can be preset to a maximum count of seven with a place
value of thousands. If ÷10 is desired for the first section, Ka is
set “high”, Kb “high” and Kc “low”. Jam inputs J1, J2, J3, and J4
are used to preset the first counting section and there is no last
counting section. The intermediate counting section consists of
three cascaded BCD decade (÷10) counters presettable by
means of Jam Inputs J5 through J16.
The Mode-Select Inputs permit frequency-synthesizer
channel separations of 10, 12.5, 20, 25 or 50 parts. These
inputs set the maximum value of N at 9999 (when the first
counting section divides by 5 or 10) or 15,999 (when the first
counting section divides by 8, 4, or 2).
The three decades of the intermediate counter can be preset
to a binary 15 instead of a binary 9, while their place values
are still 1, 10, and 100, multiplied by the number of the ÷N
mode. For example, in the ÷8 mode, the number from which
counting down begins can be preset to:
3rd Decade 1500
2nd Decade 150
1st Decade 15
Last Counting Section 1000
The total of these numbers (2665) times 8 equals 12,320.
The first counting section can be preset to 7. Therefore,
21,327 is the maximum possible count in the ÷8 mode.
The highest count of the various modes is shown in the
Extended Counter Range column. Control inputs Kb and Kc
can be used to initiate and lock the counter in the “master
preset” state. In this condition the flip-flops in the counter are
preset in accordance with the jam inputs and the counter
remains in that state as long as Kb and Kc both remain low. The
counter begins to count down from the preset state when a
counting mode other than the master preset mode is selected.
The counter should always be put in the master preset mode
before the ÷5 mode is selected. Whenever the master preset
mode is used, control signals Kb = “low” and Kc = “low” must
be applied for at least 3 full clock pulses.
After Preset Mode inputs have been changed to one of the ÷
modes, the next positive-going clock transition changes an
internal flip-flop so that the countdown can begin at the
second positive-going clock transition. Thus, after an MP
(Master Preset) mode, there is always one extra count
before the output goes high. Figure 1 illustrates a total count
of 3 (÷8 mode). If the Master Preset mode is started two
clock cycles or less before an output pulse, the output pulse
will appear at the time due. If the Master Preset Mode is not
used, the counter jumps back to the “Jam” count when the
output pulse appears.
A “high” on the Latch Enable input will cause the counter
output to remain high once an output pulse occurs, and to
remain in the high state until the latch input returns to “low”.
If the Latch Enable is “low”, the output pulse will remain high
for only one cycle of the clock-input signal.