Pin-to-Pin Compatible With the Existing
TL16C550B/C
Programmable 16- or 64-Byte FIFOs to
Reduce CPU Interrupts
Programmable Auto-RTS and Auto-CTS
In Auto-CTS Mode, CTS Controls
Transmitter
In Auto-RTS Mode, Receiver FIFO Contents
and Threshold Control RTS
Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment Is on
the Same Power Drop
Capable of Running With All Existing
TL16C450 Software
After Reset, All Registers Are Identical to
the TL16C450 Register Set
Up to 16-MHz Clock Rate for Up to 1-Mbaud
Operation
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (216 –1) and Generates an Internal 16 ×
Clock
Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added or
Deleted to or From the Serial Data Stream
5-V and 3-V Operation
Register Selectable Sleep Mode and
Low-Power Mode
Independent Receiver Clock Input
Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts
Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (DC to 1 Mbits Per
Second)
False Start Bit Detection
Complete Status Reporting Capabilities
3-State Output CMOS Drive Capabilities for
Bidirectional Data Bus and Control Bus
Line Break Generation and Detection
Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, Framing Error
Simulation
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
Available in 44-Pin PLCC and 64-Pin SQFP
Industrial Temperature Range Available for
64-Pin SQFP

description
The TL16C750 is a functional upgrade of the TL16C550C asynchronous communications element (ACE),
which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up
(character or TL16C450 mode), the TL16C750, like the TL16C550C, can be placed in an alternate mode (FIFO
mode). This relieves the CPU of excessive software overhead by buffering received and transmitted characters.
The receiver and transmitter FIFOs store up to 64 bytes including three additional bits of error status per byte
for the receiver FIFO. The user can choose between a 16-byte FIFO mode or an extended 64-byte FIFO mode.
In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload
and increase system efficiency by automatically controlling serial data flow through the RTS output and the CTS
input signals (see Figure 1).
The TL16C750 performs serial-to-parallel conversion on data received from a peripheral device or modem and
parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The
ACE includes complete modem control capability and a processor interrupt system that can be tailored to
minimize software management of the communications link.
The TL16C750 ACE includes a programmable baud rate generator capable of dividing a reference clock by
divisors from 1 to (216 – 1) and producing a 16× reference clock for the internal transmitter logic. Provisions are
also included to use this 16× clock for the receiver logic. The ACE accommodates a 1-Mbaud serial rate
(16-MHz input clock) so a bit time is 1 ms and a typical character time is 10 ms (start bit, 8 data bits, stop bit).
Two of the TL16C450 terminal functions have been changed to TXRDY and RXRDY, which provide signaling
to a direct memory access (DMA) controller.