TMS320VC5509A Features
High-Performance, Low-Power, Fixed-Point
TMS320C55x Digital Signal Processor
− 9.26-, 6.95-, 5-ns Instruction Cycle Time
− 108-, 144-, 200-MHz Clock Rate
− One/Two Instruction(s) Executed per
Cycle
− Dual Multipliers [Up to 400 Million
Multiply-Accumulates per Second
(MMACS)]
− Two Arithmetic/Logic Units (ALUs)
− Three Internal Data/Operand Read Buses
and Two Internal Data/Operand Write
Buses
128K x 16-Bit On-Chip RAM, Composed of:
− 64K Bytes of Dual-Access RAM (DARAM)
8 Blocks of 4K × 16-Bit
− 192K Bytes of Single-Access RAM
(SARAM) 24 Blocks of 4K × 16-Bit
64K Bytes of One-Wait-State On-Chip ROM
(32K × 16-Bit)
8M × 16-Bit Maximum Addressable External
Memory Space (Synchronous DRAM)
16-Bit External Parallel Bus Memory
Supporting Either:
− External Memory Interface (EMIF) With
GPIO Capabilities and Glueless Interface
to:
− Asynchronous Static RAM (SRAM)
− Asynchronous EPROM
− Synchronous DRAM (SDRAM)
− 16-Bit Parallel Enhanced Host-Port
Interface (EHPI) With GPIO Capabilities
Programmable Low-Power Control of Six
Device Functional Domains
On-Chip Scan-Based Emulation Logic
On-Chip Peripherals
− Two 20-Bit Timers
− Watchdog Timer
− Six-Channel Direct Memory Access
(DMA) Controller
− Three Serial Ports Supporting a
Combination of:
− Up to 3 Multichannel Buffered Serial
Ports (McBSPs)
− Up to 2 MultiMedia/Secure Digital Card
Interfaces
− Programmable Phase-Locked Loop
Clock Generator
− Seven (LQFP) or Eight (BGA) General-
Purpose I/O (GPIO) Pins and a General-
Purpose Output Pin (XF)
− USB Full-Speed (12 Mbps) Slave Port
Supporting Bulk, Interrupt and
Isochronous Transfers
− Inter-Integrated Circuit (I2C) Multi-Master
and Slave Interface
− Real-Time Clock (RTC) With Crystal
Input, Separate Clock Domain, Separate
Power Supply
− 4-Channel (BGA) or 2-Channel (LQFP)
10-Bit Successive Approximation A/D
IEEE Std 1149.1† (JTAG) Boundary Scan
Logic
Packages:
− 144-Terminal Low-Profile Quad Flatpack
(LQFP) (PGE Suffix)
− 179-Terminal MicroStar BGA (Ball Grid
Array) (GHH Suffix)
− 179-Terminal Lead-Free MicroStar BGA
(Ball Grid Array) (ZHH Suffix)
1.2-V Core (108 MHz), 2.7-V – 3.6-V I/Os
1.35-V Core (144 MHz), 2.7-V – 3.6-V I/Os
1.6-V Core (200 MHz), 2.7-V – 3.6-V I/Os