Ultra-low power consumption technology
• VDD = single power supply voltage of 1.6 to 5.5 V
• HALT mode
• STOP mode
High-speed wakeup from the STOP mode is possible.
• SNOOZE mode
RL78 CPU core
• CISC architecture with 3-stage pipeline
• The minimum instruction execution time can be
changed from high to ultra-low speed.
– High speed: 0.03125 μs at 32-MHz operation
with the high-speed on-chip oscillator clock
– Ultra-low speed: 30.5 μs at 32.768-kHz
operation with the subsystem clock
• Multiply/divide/multiply & accumulate instructions are supported.
• Address space: 1 MB
• General-purpose registers:
(8-bit register × 8) × 4 banks
• On-chip RAM: 12 to 48 KB
Code flash memory
• Code flash memory: 96 to 768 KB
• Block size: 2 KB
• Prohibition of block erase and rewriting (security function)
• On-chip debugging
• Self-programming (with boot swapping and flash shield window)
Data flash memory
• Data flash memory: 8 KB
• Background operation (BGO):
Instructions can be executed from the program
memory while rewriting the data flash memory.
• Number of rewrites: 1,000,000 times (typ.)