▪ Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz
▪ Two differential inputs support LVPECL, LVDS, LVHSTL,
HCSL, or LVCMOS reference clocks
▪ Generates 8 differential or 16 LVCMOS outputs
▪ Outputs arranged in two banks of four outputs each
▪ Select pins control which input drives which of two output banks
▪ Controlled by 3-level input pins that are 3.3V tolerant for all
core voltages
▪ Output type may be selected from LVPEC, LVDS or 2xLVCMOS
▪ Each bank supports a separate power supply of 3.3V, 2.5V, or 1.8V
▪ LVCMOS outputs are limited to 125MHz maximum and support
swings of 3.3V, 2.5V, 1.8V, and 1.5V
▪ Individual output enables and output type selection supported
▪ Output noise floor of –158dBc/Hz at 156.25MHz
▪ Core voltage supply of 3.3V, 2.5V, or 1.8V
▪ –40°C to 85°C ambient operating temperature
▪ Lead-free (RoHS 6) QFN-32 (5 × 5mm) packaging