FEATURES
Low phase noise phase-locked loop core Reference input frequencies to 250 MHz Programmable dual-modulus prescaler
Programmable charge pump (CP) current
Separate CP supply (VCPS) extends tuning range
Two 1.6 GHz, differential clock inputs 5 programmable dividers, 1 to 32, all integers Phase select for output-to-output coarse delay adjust 3 independent 1.2 GHz LVPECL outputs
Additive output jitter 225 fs rms
2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs
Additive output jitter 275 fs rms
Fine delay adjust on 1 LVDS/CMOS output
Serial control port
Space-saving 48-lead LFCSP

APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers
High performance instrumentation
Broadband infrastructure