General description
The LPC540xx is a family of ARM Cortex-M4 based microcontrollers for embedded
applications featuring a rich peripheral set with very low power consumption and
enhanced debug features.
The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power
consumption, enhanced debug features, and a high level of support block integration. The
ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A
hardware floating-point processor is integrated into the core.
The LPC540xx family includes 360 KB of on-chip SRAM, a quad SPI Flash Interface
(SPIFI) for expanding program memory, one high-speed and one full-speed USB host and
device controller, Ethernet AVB, LCD controller, Smart Card Interfaces, SD/MMC, CAN
FD, an External Memory Controller (EMC), a DMIC subsystem with PDM microphone
interface and I2S, five general-purpose timers, SCTimer/PWM, RTC/alarm timer,
Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), ten flexible serial
communication peripherals (USART, SPI, I2S, I2C interface), Secure Hash Algorithm
(SHA), 12-bit 5.0 Msamples/sec ADC, and a temperature sensor.
Features and benefits
 ARM Cortex-M4 core (version r0p1):
 ARM Cortex-M4 processor, running at a frequency of up to 180 MHz.
 Floating Point Unit (FPU) and Memory Protection Unit (MPU).
 ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
 Non-maskable Interrupt (NMI) input with a selection of sources.
 Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators,
and four watch points. Includes Serial Wire Output and ETM Trace for enhanced
debug capabilities, and a debug timestamp counter.
 System tick timer.
 On-chip memory:
 Up to 360 KB total SRAM consisting of 160 KB contiguous main SRAM and an
additional 192 KB SRAM on the I&D buses. 8 KB of SRAM bank intended for USB
traffic.