GENERAL DESCRIPTION
The ADSP-2184 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.
The ADSP-2184 combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory.

FEATURES
PERFORMANCE
   25 ns Instruction Cycle Time 40 MIPS Sustained
      Performance
   Single-Cycle Instruction Execution
   Single-Cycle Context Switch
   3-Bus Architecture Allows Dual Operand Fetches in
      Every Instruction Cycle
   Multifunction Instructions
   Power-Down Mode Featuring Low CMOS Standby
      Power Dissipation with 200 Cycle Recovery from
      Power-Down Condition
   Low Power Dissipation in Idle Mode

INTEGRATION
   ADSP-2100 Family Code Compatible, with Instruction
      Set Extensions
   20K Bytes of On-Chip RAM, Configured as
      4K Words On-Chip Program Memory RAM and
      4K Words On-Chip Data Memory RAM
   Dual Purpose Program Memory for Both Instruction
      and Data Storage
   Independent ALU, Multiplier/Accumulator and Barrel
      Shifter Computational Units
   Two Independent Data Address Generators
   Powerful Program Sequencer Provides
      Zero Overhead Looping Conditional Instruction
      Execution
   Programmable 16-Bit Interval Timer with Prescaler
   100-Lead LQFP

YSTEM INTERFACE
   16-Bit Internal DMA Port for High Speed Access to
      On-Chip Memory (Mode Selectable)
   4 MByte Byte Memory Interface for Storage of Data
      Tables and Program Overlays (Made Selectable)
   8-Bit DMA to Byte Memory for Transparent Program
      and Data Memory Transfers (Mode Selectable)
   I/O Memory Interface with 2048 Locations Supports
      Parallel Peripherals (Mode Selectable)
   Programmable Memory Strobe and Separate I/O Memory
      Space Permits “Glueless” System Design
      (Mode Selectable)
   Programmable Wait State Generation
   Two Double-Buffered Serial Ports with Companding
      Hardware and Automatic Data Buffering
   Automatic Booting of On-Chip Program Memory from
      Byte-Wide External Memory, e.g., EPROM, or
      Through Internal DMA Port
   Six External Interrupts
   13 Programmable Flag Pins Provide Flexible System
      Signaling
   UART Emulation through Software SPORT Reconfiguration
   ICE-Port™ Emulator Interface Supports Debugging
      in Final Systems