■ DESCRIPTION
The MB91260B series is a 32-bit RISC microcontroller designed by Fujitsu for embedded control applications which require high-speed processing.
The CPU is used the FR family and the compatibility of FR60Lite.

■ FEATURES
• FR60Lite CPU
    • 32-bit RISC, load/store architecture with a five-stage pipeline
    • Maximum operating frequency : 33 MHz (oscillation frequency 4.192 MHz, oscillation frequency 8-multiplier (PLL clock multiplication method)
    • 16-bit fixed length instructions (basic instructions)
    • Execution speed of instructions : 1 instruction per cycle
    • Memory-to-memory transfer, bit handling, barrel shift instructions, etc : Instructions suitable for embedded applications
    • Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language
    • Register interlock function : Facilitates coding in assembler.
    • Built-in multiplier with instruction-level support
        • 32 bit multiplication with sign : 5 cycles
        • 16 bit multiplication with sign : 3 cycles
    • Interrupt (PC, PS save) : 6 cycles, 16 priority levels
    • Harvard architecture allowing program access and data access to be executed simultaneously
    • FR family instruction compatible

• Internal peripheral functions
    • Capacity of internal ROM and ROM type
        MASK ROM : 128 KB (MB91263B)
        FLASH ROM : 256 KB (MB91F264B)
    • Capacity of internal RAM : 8 KB
    • A/D converter (sequential comparison type)
    • Resolution : 10 bits : 2 ch × 2 units, 8 ch × 1 unit
    • Conversion time : 1.2 µs (Minimum conversion time system clock at 33 MHz)
        1.35 µs (Minimum conversion time system clock at 20 MHz)
    • External interrupt input : 10 ch
    • Bit search module (for REALOS)
        Function for searching the MSB in each word for the first 1-to-0 inverted bit position
    • UART (Full-duplex double buffer) : 3 ch
        Selectable parity On/Off
        Asynchronous (start-stop synchronized) or clock-synchronous communications selectable
        Internal timer for dedicated baud rate (U-Timer) on each channel
        External clock can be used as transfer clock
        Error detection function for parity, frame and overrun errors
    • 8/16-bit PPG timer : 16 ch (at 8-bit) / 8 ch (at 16-bit)
    • Reload timer : 3 ch (with cascade mode, without output of reload timer 0)
    • Free-run timer : 1 ch
    • PWC timer : 2 ch
    • Input capture : 4 ch (interface with free-run timer)
    • Output compare : 6 ch (interface with free-run timer)
    • Waveform generator
        Various waveforms which are generated by using output compare, 16-bit PPG timer 0 and 16-bit dead timer
    • SUM of products macro (simple DSP)
        RAM : instruction RAM 256 × 16-bit
        XRAM 64 × 16-bit
        YRAM 64 × 16-bit
        Execution of 1 cycle product addition (16-bit × 16-bit + 40 bits)
        Operation results are extracted rounded from 40 to 16 bits
    • DMAC (DMA Controller) : 5 ch
        Operation of transfer and activation by internal peripheral interrupts and software
    • Watchdog timer
    • Low Power Consumption Mode
        Sleep/stop function
    • Package : QFP-100, LQFP-100
    • Technology : CMOS 0.35 µm
    • Power supply : 1-power supply [Vcc = 4.0 V to 5.5 V]