SL28748

DOC#: SP-AP-0017 (Rev. AA)

Page 3 of 19

promptly achieve optimum compliance and clock signal

integrity; historically, attainable typically through device and/or

board redesigns.

hard coded.

Features:

- > 4000 bits of configurations

- Can be configured through SMBus or hard coded

- Custom frequency sets

- Differential skew control on true or compliment or both

- Differential duty cycle control on true or compliment or both

- Differential amplitude control

- Differential and single-ended slew rate control

- Program Internal or External series resistor on single-ended

clocks

- Program different spread profiles

- Program different spread modulation rate

Frequency Select Pin FS

Apply the appropriate logic levels to FS inputs before

CKPWRGD assertion to achieve host clock frequency

selection. When the clock chip sampled HIGH on CKPWRGD

and indicates that VTT voltage is stable then FS input values

are sampled. This process employs a one-shot functionality

and once the CKPWRGD sampled a valid HIGH, all other FS,

and CKPWRGD transitions are ignored except in test mode.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers are individually enabled or disabled. The

registers associated with the Serial Data Interface initialize to

their default setting at power-up. The use of this interface is

optional. Clock device register changes are normally made at

system initialization, if any are required. The interface cannot

be used during system operation for power management

functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, access the bytes in sequential

order from lowest to highest (most significant bit first) with the

ability to stop after any complete byte is transferred. For byte

write and byte read operations, the system controller can

access individually indexed bytes. The offset of the indexed

byte is encoded in the command code described in Table 1.

The block write and block read protocol is outlined in Table 2

while Table 3 outlines byte write and byte read protocol. The

slave receiver address is 11010010 (D2h).

.

Frequency Select Pin (FS)

FS

CPU

Power On

SRC

SATA

DOT96

27MHz

REF

0

133MHz

Default

100MHz

100MHz

96MHz

27MHz

14.318MHz

1

100MHz

Table 1. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

1Start

1

Start

8:2

Slave address–7 bits

8:2

Slave address–7 bits

9

Write

9

Write

10

Acknowledge from slave

10

Acknowledge from slave

18:11

Command Code–8 bits

18:11

Command Code–8 bits

19

Acknowledge from slave

19

Acknowledge from slave

27:20

Byte Count–8 bits

20

Repeat start

28

Acknowledge from slave

27:21

Slave address–7 bits