RFHCS362F datasheet(32/60 Pages) MICROCHIP

32 / 60 page

rfHCS362G/362F

DS41189A-page 32

Preliminary

6.4

Clock Output (CLKOUT)

The crystal oscillator feeds a divide-by-four circuit that

provides a clock output at the CLKOUT pin. CLKOUT

is slew-rate limited in order to keep spurious signal

emissions as low as possible. The voltage swing

(VCLKOUT) depends on the capacitive loading (CLOAD)

on the CLKOUT pin (2 VPP at 5 pF).

6.5

Phase-Locked Loop (PLL)

The PLL consists of a Phase-frequency Detector

(PFD), charge pump, Voltage-controlled Oscillator

(VCO), and fixed divide-by-32 divider. An external loop

filter is connected to pin LF. The loop filter controls the

dynamic behavior of the PLL, primarily lock time and

spur levels. The application determines the loop filter

requirements.

The rfHCS362 employs a charge pump PLL that offers

many advantages over the classical voltage phase

detector PLL: infinite pull-in range and zero steady

state phase error. The charge pump PLL allows the use

of passive loop filters that are lower cost and minimize

noise. Charge pump PLLs have reduced flicker noise

thus limiting phase noise. Many of the classical texts on

PLLs do not cover this type of PLL, however, today this

is the most common type of PLL. This data sheet briefly

covers the general terms and design requirements for

the rfPIC. Detailed PLL design and operation is beyond

the scope of this data sheet. For more information, the

designer is referred to "

PLL Performance, Simulation,

and Design," Second Edition by Dean Banerjee ISBN

0970820704. Banerjee covers charge pump PLLs and

loop filter selection.

The loop filter has a major impact on lock time and spur

levels. Lock time is the time it takes the PLL to lock on

frequency. When the PLL is first powered on or is

changing frequencies, no data can be transmitted.

Lock time must be considered before data transmission

can begin. In addition to PLL lock time, the designer

must take into account the crystal oscillator start time of

approximately 1 ms. See Section 6.3 for more informa-

tion about the crystal oscillator. Reference spurs occur

at the carrier frequency plus and minus integer multi-

ples of the reference frequency. Phase noise refers to

noise generated by the PLL. Spur levels and phase

noise can increase the signal to noise ratio (SNR) of

the system and mask or degrade the transmitted sig-

nal.

The first order effect on PLL performance is loop band-

width. Loop bandwidth (

c) is defined as the point

where the open loop phase transfer function equals 0

dB. Selecting a small loop bandwidth results in lower

spur levels but slower lock time. Selecting a larger loop

bandwidth results in a faster lock time but higher spur

levels.

Second order effects on PLL performance is Phase

margin (

φ) and Damping factor (ζ). Phase margin is a

measure of PLL stability. Choosing a phase margin that

is too low will result in PLL instability. Choosing a higher

phase margin results in less ringing and faster lock time

at the expense of higher spur levels. Loop filters are

typically designed for a total phase margin between 30

and 70 degrees. The aim of the designer is to choose

a loop bandwidth and phase margin that gives the fast-

est possible lock time and meets the spur level require-

ments of the application.

Damping factor governs the second order transient

response that determines the shape of the exponential

envelope of the natural frequency. The natural fre-

quency, also called ringing frequency, is the frequency

of the VCO steering voltage as the PLL settles. Lock

time is proportional to damping factor and inversely

proportional to loop bandwidth.

The application determines the loop filter component

requirements. For example, if the transmit frequency

selected is near band edges or restricted bands, spur

levels must be reduced to meet regulatory require-

ments. However, this will be at the expense of lock

time. For an FSK application, a larger damping factor (

≅

1.0) is desired so that there is less overshoot in the key-

ing of FSK. For an ASK application, a damping factor =

0.707 results in less settling time and near optimum

noise performance.

Figure 6-4 shows an example passive second order

loop filter circuit. Table 6-4 gives example loop filter val-

ues for a crystal frequency of 13.56 MHz and transmit

frequency of 433.92 MHz. Table 6-5 gives example

loop filter values for a crystal frequency of 9.84375

MHz and transmit frequency of 315 MHz.

Layout considerations - Shield each side of the clock

output trace with ground traces to isolate the CLK-

OUT signal and reduce coupling.

Layout considerations - Keep traces short and place

loop filter components as close as possible to the LF

pin.

RFHCS362F Datasheet(PDF) 32 Page - Microchip Technology

RFHCS362F Datasheet(HTML) 32 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Descarga

Enlace URL