Reference Design

IRMCS2013

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9.3 Parallel Interface Port

IRMCS2013 provides an 8-bit parallel interface port to facilitate microprocessor interface. The interface is generic and

compatible with most common 8-bit parallel interfaces such as MCS8051, some Motorola 8-bit uP, MicroChip, etc.

Figure 16 shows the connection diagram. The connector J7 is a 2-by-8 connector.

Figure 16. Parallel Interface Port, J7

Each signal is 3.3V level and data bus is multiplexed. Table 3 summarizes each signal definition.

Signal

Description

HP_nCS

I

Active low Host Port Chip Select

HP_nOE

I

Active Low Host Port Output Enable

HP_nWE

I

Active low Host Port Write Enable

HP_A

I

Host Port Register Address. 1 = Address register, 0 = Data Register

HP_Dn

I/O

Bidirectional Host Port data bus, where n = data bit 0 - 7

Table 3. Microprocessor Interface Module Signal Definitions

Figure 17 and Table 4 show read cycle timing for the host parallel interface. Figure 18 and Table 5 show write cycle

timing.