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ICS8725 Datasheet(PDF) 1 Page - Integrated Circuit Systems

No. de pieza ICS8725
Descripción Electrónicos  DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
PDF  7 Pages
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Fabricante Electrónico  ICST [Integrated Circuit Systems]
Página de inicio  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS8725 Datasheet(HTML) 1 Page - Integrated Circuit Systems

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8725
www.icst.com/products/hiperclocks.html
REV. A MARCH 5, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8725
1-TO-5
DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
PRELIMINARY
GENERAL DESCRIPTION
The ICS8725 is a high performance LVHSTL
zero delay buffer and a member of the
HiPerClockS™ family of High Performance
Clocks Solutions from ICS. The VCO operates
at a frequency range of 250MHz to 500MHz.
Utilizing one of the outputs as feedback to the PLL output
frequencies up to 500MHz can be regenerated with zero
delay with respect to the input. Dual reference clock inputs
support redundant clock or multiple reference applications.
BLOCK DIAGRAM
PIN ASSIGNMENT
FEATURES
• Fully integrated PLL
• 5 LVHSTL outputs each with the ability to drive 50Ω to
ground
• Voh (max) = 1.2V
• 31.25MHz to 500MHz output frequency range
• Spread Smart™ for regenerating spread spectrum clocks
• Differential reference clock inputs accept any differential
input signal
•· Differential reference clock inputs will accept single ended
input signal with one of the inputs biased with a resistor
network
• 31.25MHz to 622MHz input frequency range
• LVCMOS / LVTTL control inputs
• 3.3V core, 1.8V output operating supply voltage
• 32 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.8mm package lead pitch
• 0°C to 70°C ambient operating temperature
• Industrial temperature version available upon request
HiPerClockS™
,&6
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
DIV_SEL0
DIV_SEL1
REF_CLK1
nREF_CLK1
REF_CLK2
nREF_CLK2
REF_SEL
REF_DIV
FB_IN
nFB_IN
PLL_SEL
MR
0
1
PLL
÷1
÷2
÷4
÷8
0
1
÷8
0
1
32 31 30 29 28 27 26 25
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VDDO
Q3
nQ3
Q2
nQ2
Q1
nQ1
VDDO
DIV_SEL0
DIV_SEL1
REF_CLK1
nREF_CLK1
REF_CLK2
nREF_CLK2
REF_SEL
MR
32-Lead LQFP
Y Package
Top View
ICS8725


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