LP3989-01

Aug.-2014

www.lowpowersemi.com

Page 6 of 8

Preliminary Datasheet

LP3989

Applications Information

L

ike any low-dropout regulator, the external capacitors

used with the LP3989 must be carefully selected for

regulator stability and performance. Using a capacitor

whose value is > 2µF on the LP3989 input and the

amount of capacitance can be increased without limit.

The input capacitor must be located a distance of not

more than 0.5 inch from the input pin of the IC and

returned to a clean analog ground. There is a special

attention which is the input capacitance should not be

less than output capacitance. Any good quality

ceramic or tantalum can be used for this capacitor.

The capacitor with larger value and lower ESR

(equivalent series resistance) provides better PSRR

and line-transient response. The output capacitor must

meet both requirements for minimum amount of

capacitance and ESR in all LDOs application. The

LP3989 is designed specifically to work with low ESR

ceramic output capacitor in space-saving and

performance consideration. Using a ceramic capacitor

whose value is at least 1µF with ESR is > 25mΩ on the

LP3989 output ensures stability. The LP3989 still

works well with output capacitor of other types due to

the wide stable ESR range. Output capacitor of larger

capacitance can reduce noise and improve load

transient response, stability, and PSRR. The output

capacitor should be located not more than 0.5 inch

clean analog ground.

Start-up Function Enable Function

The LP3989 features an LDO regulator enable/disable

function. To assure the LDO regulator will switch on,

the EN turn on control level must be greater than 1.4

volts but not above Vin+0.3V. The LDO regulator will

go into the shutdown mode when the voltage on the

EN pin falls below 0.4 volts. For protecting the system,

the LP3989 have a quick-discharge function. If the

enable function is not needed in a specific application,

continuously on state.

Feedback Capacitor and Voltage

For adjustable version, connecting a 22pF between

output pin and FB pin significantly reduces output

voltage ripple, it is critical that the capacitor connection

should be direct and PCB traces should be as short as

possible.

The output voltage of LDO could be set by the formula

below: