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STR710FZ2T6 Datasheet(PDF) 36 Page - STMicroelectronics |
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STR710FZ2T6 Datasheet(HTML) 36 Page - STMicroelectronics |
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36 / 49 page  STR71xF - ELECTRICAL CHARACTERISTICS 36/49 Table 18. PLL2 Electrical Characteristics fFREE1 PLL free running frequency FREF_RANGE = 0 MX[1:0]=’01’ or ‘11’ 1MHz FREF_RANGE = 0 MX[1:0]=’00’ or ‘10’ 2MHz FREF_RANGE = 1 MX[1:0]=’01’ or ‘11’ 2MHz FREF_RANGE = 1 MX[1:0]=’00’ or ‘10’ 4MHz tLOCK1 PLL lock time FREF_RANGE = 0 Stable Input Clock Stable V33IOPLL, V18 300 µs FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 600 µs ∆tJITTER1 PLL jitter (peak to peak) tPLL = 4 MHz, MX[1:0]=’11’ Global Output division = 32 (Output Clock = 2 MHz) 0.7 2 ns Symbol Parameter Test Conditions Value Unit Min Typ Max fPLLCLK2 PLL output clock fPLL x 28 140 MHz fPLL2 PLL input clock FREF_RANGE = 0 1.5 3.0 MHz FREF_RANGE = 1 3.0 5 MHz tLOCK2 PLL lock time FREF_RANGE = 0 Stable Input Clock Stable V33IOPLL, V18 300 µs FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 600 µs ∆tJITTER2 PLL jitter (peak to peak) tPLL = 4 MHz, MX[1:0]=’11’ Global Output division = 32 (Output Clock = 2 MHz) 0.7 2 ns Symbol Parameter Test Conditions Value Unit Min Typ Max |
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