ICS951901 datasheet(4/19 Pages) ICST | Programmable Frequency Generator & Integrated Buffers for Pentium III Processor

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ICS951901 Datasheet(PDF) 4 Page - Integrated Circuit Systems

No. de pieza	ICS951901

Descripción Electrónicos	Programmable Frequency Generator & Integrated Buffers for Pentium III Processor

PDF	19 Pages

Scroll/Zoom	100%

Fabricante Electrónico	ICST [Integrated Circuit Systems]

Página de inicio	http://www.icst.com

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ICS951901 Datasheet(HTML) 4 Page - Integrated Circuit Systems

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4

ICS951901

0670B—07/15/04

Byte 1: CPU, Active/Inactive Register

(1= enable, 0 = disable)

Byte 2: PCI, Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

d

e

v

r

e

s

e

R

6

t

i

B-

1

d

e

v

r

e

s

e

R

5

t

i

B3

11

4

K

L

C

I

C

P

4

t

i

B2

11

3

K

L

C

I

C

P

3

t

i

B1

11

2

K

L

C

I

C

P

2

t

i

B0

11

1

K

L

C

I

C

P

1

t

i

B9

1

0

K

L

C

I

C

P

0

t

i

B8

1

F

_

K

L

C

I

C

P

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

2. Latched Frequency Selects (FS#) will be inverted logic

load of the input frequency select pin conditions.

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

d

e

v

r

e

s

e

R

6

t

i

B1

21

z

H

M

8

4

_

4

2

5

t

i

B0

21

z

H

M

8

4

4

t

i

B6

21

2

1

M

A

R

D

S

3

t

i

B7

21

1

1

M

A

R

D

S

2

t

i

B8

21

0

1

M

A

R

D

S

1

t

i

B0

31

9

M

A

R

D

S

0

t

i

B1

31

8

M

A

R

D

S

Byte 4: SDRAM , Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

X

)

k

c

a

b

d

a

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(

3

S

F

6

t

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B-

X

)

k

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a

b

d

a

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(

2

S

F

5

t

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)

k

c

a

b

d

a

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(

1

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4

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k

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0

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F

3

t

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B3

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F

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R

2

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B2

1

1

F

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R

1

t

i

B7

11

1

K

L

C

P

G

A

0

t

i

B6

11

0

K

L

C

P

G

A

Byte 5: AGP, Active/Inactive Register

(1= enable, 0 = disable)

Byte 3: SDRAM, Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

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B3

31

7

M

A

R

D

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6

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B4

31

6

M

A

R

D

S

5

t

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B6

31

5

M

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D

S

4

t

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B7

31

4

M

A

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D

S

3

t

i

B8

31

3

M

A

R

D

S

2

t

i

B0

41

2

M

A

R

D

S

1

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B1

41

1

M

A

R

D

S

0

t

i

B2

41

0

M

A

R

D

S

T

I

B#

N

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W

PN

O

I

T

P

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C

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7

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i

B-

1

8

4

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4

2

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H

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8

4

:

0

,

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H

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2

:

1

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6

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B7

41

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B6

41

1

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P

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1

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B5

41

2

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C

U

P

C

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1

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