ISL6277HRZ datasheet(18/37 Pages) RENESAS

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ISL6277

FN8270 Rev 1.00

Page 18 of 37

Mar 8, 2012

The ISL6277 will adjust the phase pulse-width relative to the

other phases to make VISEN1 =VISEN2 =VISEN3, thus to achieve

IL1 =IL2 =IL3, when Rdcr1 =Rdcr2 =Rdcr3 and

Rpcb1 =Rpcb2 =Rpcb3.

Using the same components for L1, L2 and L3 provides a good

match of Rdcr1, Rdcr2 and Rdcr3. Board layout determines Rpcb1,

Rpcb2 and Rpcb3. It is recommended to have a symmetrical

layout for the power delivery path between each inductor and the

output voltage rail, such that Rpcb1 =Rpcb2 =Rpcb3.

Sometimes, it is difficult to implement symmetrical layout. For

the circuit shown in Figure 15, asymmetric layout causes

different Rpcb1, Rpcb2 and Rpcb3 values, thus creating a current

imbalance. Figure 16 shows a differential sensing current

balancing circuit recommended for ISL6277. The current sensing

traces should be routed to the inductor pads so they only pick up

the inductor DCR voltage. Each ISEN pin sees the average voltage

of three sources: its own, phase inductor phase-node pad, and

the other two phase inductor output side pads. Equations 8

through 10 give the ISEN pin voltages:

The ISL6277 will make VISEN1 = VISEN2 = VISEN3 as shown in

Equations 11 and 12:

Rewriting Equation 11 gives Equation 13:

Rewriting Equation 12 gives Equation 14:

Combining Equations 13 and 14 gives:

Therefore:

Current balancing (IL1 =IL2 =IL3) is achieved when

Rdcr1 =Rdcr2 =Rdcr3. Rpcb1, Rpcb2 and Rpcb3 do not have any

effect.

Since the slave ripple capacitor voltages mimic the inductor

currents, the R3™ modulator can naturally achieve excellent

current balancing during steady state and dynamic operations.

Figure 17 shows the current balancing performance of the

evaluation board with load transient of 12A/51A at different rep

rates. The inductor currents follow the load current dynamic

change with the output capacitors supplying the difference. The

inductor currents can track the load current well at a low

repetition rate, but cannot keep up when the repetition rate gets

into the hundred-kHz range, where it is out of the control loop

bandwidth. The controller achieves excellent current balancing in

all cases installed.

FIGURE 16. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT

INTERNAL

TO IC

ISEN3

Risen

Cisen

ISEN2

Risen

Cisen

ISEN1

Risen

Cisen

Rdcr3

Rdcr2

Rdcr1

PHASE3

PHASE2

PHASE1

IL3

IL2

IL1

Rpcb3

Rpcb2

Rpcb1

Risen

V3p

V3n

V2p

V2n

V1p

V1n

VISEN1

V1p V2n V3n

(EQ. 8)

VISEN2

V1n V2p V3n

(EQ. 9)

VISEN3

V1n V2n V3p

(EQ. 10)

V1p V2n V3n

V1n V2p V3n

(EQ. 11)

V1n V2p V3n

V1n V2n V3p

(EQ. 12)

V1p V1n

–

V2p V2n

–

(EQ. 13)

V2p V2n

–

V3p V3n

–

(EQ. 14)

V1p V1n

–

V2p V2n

–

V3p V3n

–

(EQ. 15)

Rdcr1 IL1



Rdcr2 IL2



Rdcr3 IL3



(EQ. 16)

ISL6277HRZ Datasheet(PDF) 18 Page - Renesas Technology Corp

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