ADN2891

Data Sheet

Rev. B | Page 12 of 16

PCB Layout

Figure 21 shows the recommended PCB layout. The 50 Ω

transmission lines are the traces that bring the high frequency

input and output signals (PIN, NIN, OUTP, and OUTN) to the

SMA connectors with minimum reflection. To avoid a signal

skew between the differential traces, each differential PIN/NIN

and OUTP/OUTN pair should have matched trace lengths from

the signal pins to the corresponding SMA connectors. C1, C2,

C3, and C4 are ac coupling capacitors in series with the high

speed, signal input/output paths. To minimize the possible

mismatch, the ac coupling capacitor pads should be the same

width as the 50 Ω transmission line trace width. To reduce

supply noise, a 1 nF decoupling capacitor should be placed on

the same layer as close as possible to the VCC pins. A 0.1 µF

decoupling capacitor can be placed on the bottom of the PCB

directly underneath the 1 nF capacitor. All high speed, CML

outputs have internal 50 Ω resistor termination between the

output pin and VCC. The high speed inputs, PIN and NIN, also

have the internal 50 Ω termination to an internal reference

voltage.

As with any high speed, mixed-signal design, keep all high

speed digital traces away from sensitive analog nodes.

Soldering Guidelines for the LFCSP

The lands on the 16-lead LFCSP are rectangular. The PCB pad

for these should be 0.1 mm longer than the package land length

and 0.05 mm wider than the package land width. The land

should be centered on the pad. This ensures that the solder joint

size is maximized. The bottom of the LFCSP has a central

exposed pad. The pad on the printed circuit board should be at

least as large as the exposed pad. Users must connect the

exposed pad to VEE using filled vias so that solder does not

leak through the vias during reflow. This ensures a solid

connection from the exposed pad to VEE.

1

VIAS TO

GND

EXPOSED PAD

PIN

NIN

VIA TO C12, R2

ON BOTTOM

C11

VIA TO BOTTOM

C3

C8

C4

C1

C6

C2

OUTP

DOUBLE-VIAS TO REDUCE

INDUCTANCE TO SUPPLY

AND GND

R1, C9, C10 ON BOTTOM

TO ROSA

PLACE C7 ON

BOTTOM OF BOARD

UNDERNEATH C8

OUTN

PLACE C5 ON

BOTTOM OF BOARD

UNDERNEATH C6

DOUBLE-VIA TO GND

TO REDUCE INDUCTANCE

Figure 21. Recommended PCB Layout (Top View)