ADCMP581BCPZ-R2 datasheet(8/16 Pages) AD

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ADCMP580/ADCMP581/ADCMP582

Data Sheet

Rev. B | Page 8 of 16

VTP

VTN

VCCO

ADCMP582

TOP VIEW

NOTES

1. THE METALLIC BACK SURFACE OF THE PACKAGE IS NOT ELECTRICALLY

CONNECTED TO ANY PART OF THE CIRCUIT. IT CAN BE LEFT FLOATING FOR

OPTIMAL ELECTRICAL ISOLATION BETWEEN THE PACKAGE HANDLE AND

THE SUBSTRATE OF THE DIE. IT CAN ALSO BE SOLDERED TO THE

APPLICATION BOARD IF IMPROVED THERMAL AND/OR MECHANICAL

STABILITY IS DESIRED.

Figure 4. ADCMP582 Pin Configuration

Table 5. ADCMP582 Pin Function Descriptions

Pin No.

Mnemonic

Description

VTP

Termination Resistor Return Pin for VP Input.

Noninverting Analog Input.

Inverting Analog Input.

VTN

Termination Resistor Return Pin for VN Input.

5, 16

VCCI

Positive Supply Voltage.

Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of the

comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator being

placed into latch mode. LE must be driven in complement with LE.

Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the input

of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the comparator being

placed into latch mode. LE must be driven in complement with LE.

VTT

Termination Return Pin for the LE/LE Input Pins. For the ADCMP582 (PECL output stage), connect this pin to the

VCCO –2 V termination potential.

9, 12

VCCO

Digital Ground Pin/Positive Logic Power Supply Terminal. This pin must be connected to the positive logic power

VCCO supply.

Inverting Output. Q is logic low if the analog voltage at the noninverting input, VP, is greater than the analog

voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions

(Pin 6 to Pin 7) for more information.

Noninverting Output. Q is logic high if the analog voltage at the noninverting input, VP, is greater than the analog

voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions

(Pin 6 to Pin 7) for more information.

VEE

Negative Power Supply.

HYS

Hysteresis Control. Leave this pin disconnected for zero hysteresis. Connect this pin to the VEE supply with a

suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 8 for proper sizing of the HYS

hysteresis control resistor.

GND

Analog Ground.

EPAD

Exposed Pad. The metallic back surface of the package is not electrically connected to any part of the circuit. It

can be left floating for optimal electrical isolation between the package handle and the substrate of the die. It

can also be soldered to the application board if improved thermal and/or mechanical stability is desired.

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