M41ST95Y*, M41ST95W

8/35

Figure 7. Hardware Hookup

Note: 1. CPOL (Clock Polarity) and CPHA (Clock Phase) are bits that may be set in the SPI Control Register of the MCU.

AI06372

Master

(ST6, ST7, ST9,

ST10, Others)

SPI Interface with

(CPOL, CPHA)(1) =

('0','0') or ('1','1')

D

Q

C

CS3

CS2

CS1

M41ST95Y/W

E

XXXXX

CQD

XXXXX

CQD

E

E

CQD