CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

4

POST OFFICE BOX 655303

control pin settings

The CDCM1802 has three control pins, S0, S1, and the enable pin (EN) to select different output mode settings.

All three inputs (S0, S1, EN) are 3-level inputs. In addition, the EN input allows disabling all outputs and place

them into a high-z (or tristate) output state when pulled to GND.

EN

CDCM1802

S1

S0

Setting for Mode 4:

S1 = 0

S0 = 1

Figure 1. Control Pin Setting for Example

Each control input incorporates a 60-kΩ pullup resistor. Thus, it is easy to choose the input setting by designing

a resistor pad between the control input and GND. To choose a logic zero, the resistor value must be zero.

Setting the input high requires leaving the resistor pad empty (no resistor installed). For setting the input to

Table 1. Selection Mode Table

LVPECL

LVCMOS

MODE

EN

S1

S0

Y0

Y1

0

0

X

X

Off (high-z)

Off (high-z)

1

0

÷ 1

÷ 1

2

1

÷ 1

÷ 2

3

1

0

0

÷ 1

÷ 4

4

0

1

÷ 2

÷ 2

5

1

0

1

÷ 2

÷ 4

6

0

0

÷ 4

÷ 4

7

1

0

÷ 4

÷ 8

8

÷ 8

÷ 1

9

1

1

0

÷ 8

÷ 4

10

1

1

1

Off (high-z)

÷ 4

NOTE: The LVPECL outputs are open emitter stages. Thus, if you leave the unused

LVPECL output Y0 unconnected, then the current consumption is minimized and

noise impact to remaining outputs is neglectable. Also, each output can be