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APL6002 Datasheet(PDF) 3 Page - Anpec Electronics Coropration

No. de pieza APL6002
Descripción Electrónicos  Low-Power, 8-bit, 3-Channel Analog to Digital Converters
PDF  17 Pages
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Fabricante Electrónico  ANPEC [Anpec Electronics Coropration]
Página de inicio  http://www.anpec.com.tw
Logo ANPEC - Anpec Electronics Coropration

APL6002 Datasheet(HTML) 3 Page - Anpec Electronics Coropration

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Copyright
© ANPEC Electronics Corp.
Rev. A.3 - Jun., 2017
APL6002
www.anpec.com.tw
3
Electrical Characteristics
Unless otherwise specified, these specifications apply over V
DD=5V, and TJ= -40 to 85
oC. Typical values are at T
J=25
oC.
Specification
Sym bol
Param eter
Te st condition
Min.
Typ.
Ma x.
Unit
SUP PLY CURRENT
I
VDD
V DD Input Cu rrent
-
80
100
u A
PO WER-ON RE SET (PO R)
V POR
V DD PO R Threshold Voltage
VDD Risin g
-
2.35
2 .6
V
VPOR_Hys
V DD PO R Hysteresis Vo ltag e
VDD Falling
-
0 .1
-
V
Voltage Monitor
A/D
A /D Reso lution
-
10
-
mV/LSB
A /D Fu ll S ca le Range
1
-
3.56
V
Diffe rential non linea rity
-
-
1 .5
LS B
Diffe rential non linea rity
VDD=3.6 V
-
-
2 .5
LS B
Integra l n onlin earity
-
-
1 .5
LS B
Integra l n onlin earity
VDD=3.6 V
-
-
2 .5
LS B
Inpu t Bia s Curren t
-
-
10
n A
A IN1, AIN2, AIN3 Mon ito r Time
-
0 .6
0.72
ms
Address S etting and Ale rt Output
ADDR
A ddress Latch Time
-
-
10
ms
A ddress 1 Vol tag e Ra nge
Ad dress = 0x7 E (Hex)
92
95
100
%V DD
A ddress 2 Vol tag e Ra nge
Ad dress = 0x7 C (Hex)
82
85
88
%V DD
A ddress 3 Vol tag e Ra nge
Ad dress = 0x7 A (Hex)
72
75
78
%V DD
A ddress 4 Vol tag e Ra nge
Ad dress = 0x7 8 (Hex)
63
65
68
%V DD
A ddress 5 Vol tag e Ra nge
Ad dress = 0x7 6 (Hex)
52
55
58
%V DD
A ddress 6 Vol tag e Ra nge
Ad dress = 0x7 4 (Hex)
42
45
48
%V DD
A ddress 7 Vol tag e Ra nge
Ad dress = 0x7 2 (Hex)
32
35
38
%V DD
A ddress 8 Vol tag e Ra nge
Ad dress = 0x7 0 (Hex)
0
25
28
%V DD
Whe n Ale rt/ADDR p in pull low, IALT=10 mA
-
-
0 .2
V
Al ert
A lert O utput L ow Voltage
Whe n Ale rt/ADDR p in pull low, IALT=50 mA
-
-
0 .8
V
A lert P ull Low Pulse Time
Whe n Ale rt/ADDR p in Ale rt
-
50
-
us
A lert P ull Low cycle Time
Whe n Ale rt/ADDR p in Ale rt
-
2
-
s
A lert/A DDR Leaka ge Cu rrent
VAlert/ADDR=5V
-
-
100
n A
I
2
C Interfac e
FI2C
I
2C Clock Rate Ra nge
-
-
400
kHz
I
2C Input High Voltage
1.4
-
-
V
I
2
C In put L ow Voltage
-
-
0 .4
V
I
2
C Leakag e Cu rrent
VSCL=V SDA=5 V
-
-
100
n A



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