Copyright

© ANPEC Electronics Corp.

Rev. A.3 - Jun., 2017

APL6002

www.anpec.com.tw

9

Function Description

Input Voltage and Power-On-Reset

The APL6002 can work normally and start monitoring the AINx voltage, when the supply voltage VDD is greater than the

POR. The POR threshold is 2.5V typically when the VDD rising.

The SCL voltage level can only be changed to Low to High,

when the SDA is stable unless the START and STOP status.

The SDA can only be changed the voltage level when the

SCL voltage is Low.

The START (S) condition is the SDA transient from High to

Low, when SCL is High. The STOP (P) condition is the SDA

transient from Low to High, when SCL is High. The STOP

condition must send before each START condition.

Each Address and Data are transmitted by using 8 clock

pulses with 1 clock pulse Acknowledge (A). The Acknowl-

edge is used for two purposes: one is the device that recog-

nizes its own address. Another one is all of the master and

slave to acknowledge receipt the register address or data.

The SDA will pull Low to acknowledge.

Read and Write Protocol

(S=START, P=STOP, A=ACK from Slave, NA=Non-ACK)

SDA

SCL

STOP (P)

START (S)

SDA

SCL

Bit 1

Bit 0

ACK

Slave SDA pull Low

Master SDA pull Low

SDA

SCL

7-Bit Slave Address

A

8-Bit Register Address

A

8-Bit Register Data for Address

A

S

P

MSB to LSB

MSB to LSB

MSB to LSB

Master Write to a Slave Register Example

0

(W)

SDA

SCL

7-Bit Slave Address

A

8-Bit Register Address

A

8-Bit Register Data for Address

NA

S

P

MSB to LSB

MSB to LSB

MSB to LSB

Master Read from a Slave Register Example

7-Bit Slave Address

A

MSB to LSB

S

0

(W)

1

(R)

SDA

SCL

SDA stable

SCL level Low

Data valid

Data change