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AM652X Datasheet(PDF) 210 Page - Texas Instruments |
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AM652X Datasheet(HTML) 210 Page - Texas Instruments |
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210 / 299 page  MMC1_CLK MMC1_CMD MMC1_DAT[3:0] SDR1041 SDR1042L SDR1042H SDR1045 SDR1046 SDR1045 SDR1046 MMC1_12 MMC1_CLK MMC1_CMD MMC1_DAT[3:0] SDR1044 SDR1048 SDR1043 SDR1047 SDR1041 SDR1042H SDR1042L MMC1_11 MMC1_CLK MMC1_CMD MMC1_DAT[3:0] SDR501 SDR502L SDR502H SDR505 SDR506 SDR505 SDR506 MMC1_10 210 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated Figure 5-85. MMC/SD in - High Speed SDR50 - Transmitter Mode 5.11.5.16.2.6 UHS-I SDR104, 4-bit data, half-cycle Table 5-81 presents Timing requirements and Switching characteristics for MMC1 - SDR104 in receiver and transmitter mode (see Figure 5-86 and Figure 5-87) Table 5-81. Switching Characteristics for MMC1 - SD Card SDR104 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SDR104 1 fop(clk) Operating frequency, MMC1_CLK Positive-edge Reference Clock 192 MHz SDR104 2H tw(clkH) Pulse duration, MMC1_CLK high Positive-edge Reference Clock 2.17 ns SDR104 2L tw(clkL) Pulse duration, MMC1_CLK low Negative-edge Reference Clock 2.17 ns SDR104 5 td(clkL-cmdV) Delay time, MMC1_CLK falling clock edge to MMC1_CMD transition Negative-edge Reference Clock 1.33 3.28 ns SDR104 6 td(clkL-dV) Delay time, MMC1_CLK falling clock edge to MMC1_DAT[3:0] transition Positive-edge Reference Clock 1.33 3.28 ns (1) P = output MMC1_CLK period in ns Figure 5-86. MMC/SD in - High Speed SDR104 - Receiver Mode Figure 5-87. MMC/SD in - High Speed SDR104 - Transmitter Mode |
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