AM652X datasheet(240/299 Pages) TI1

240 / 299 page

240

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Detailed Description

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Dedicated MPU clocking (Arm PLLs) for full flexibility in performance trade-offs

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Advanced power management with fine-grained control of individual A53 CPU power domains, coarse-

grained cluster-level power management, and low-power standby modes (WFI/WFE modes)

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Dedicated RTI windowed watchdog timer per core

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Support for Big-Endian (BE) and Little-Endian (LE) at core level

For more information, see section Arm Cortex-A53 Subsystem in chapter Processors and Accelerators of

the device TRM.

6.4

Arm Cortex-R5F

The MCU_ARMSS is a dual-core implementation of the Arm® Cortex-R5F® processor configured for

split/lock operation. It also includes accompanying memories (L1 caches and tightly-coupled memories),

standard Arm CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM),

ECC Aggregators, and various wrappers for protocol conversion and address translation for easy

integration into the SoC.

NOTE

The Cortex-R5F processor is a Cortex-R5 processor that includes the optional Floating Point

Unit (FPU) extension. In this TRM, all references to the Cortex-R5 processor by default apply

to the Cortex-R5F processor.

The MCU_ARMSS supports the following features:

AM652X Datasheet(PDF) 240 Page - Texas Instruments