LTC4216IDE datasheet(13/24 Pages) LINER

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LTC4216

4216f

Normal Power-Up and Power-Down

Figure 8 illustrates the timing diagram for a normal power-

up sequence in the case where a printed circuit board is

inserted into a live backplane.

At time point 1, the bias supply (VCC) ramps up and en-

ables the device when the supply voltage rises above the

undervoltage lockout threshold (2.12V). At time point 2,

SENSEP supply, together with the ON pin, ramp up and

start the ﬁrst timing cycle when the ON pin voltage exceeds

0.8V. The TIMER capacitor is allowed to ramp up with 2µA

pull-up once all these conditions are met: GATE < 0.2V,

FILTER < 0.2V, TIMER < 0.2V, SS < 0.2V. At time point 3,

TIMER reaches the VTMR(TH) threshold and the ﬁrst timing

cycle terminates. The electronic circuit breaker is enabled

and TIMER capacitor is quickly discharged. At time point

4 checks are made for TIMER, GATE, FILTER and SS <

0.2V, ∆VSENSE below 25mV and ⎯F⎯A⎯U⎯L⎯T high before a GATE

ramp-up cycle begins. GATE is held low by the analog cur-

rent limit ampliﬁer as SS capacitor ramps up with a 10µA

current source. SS switches to 1µA pull-up for a slower

ramp rate when it crosses the input offset voltage of the

ACL ampliﬁer. At this time point, the ACL ampliﬁer releases

the GATE and allows it to ramp up with a 20µA pull-up. At

time point 6, when the GATE voltage reaches the turn-on

threshold of the external MOSFET, current begins ﬂowing

into the load capacitor. The MOSFET current level at this

time point is controlled by the ACL ampliﬁer and the GATE

ramp is slowed down. SS switches the pull-up current

from 1µA to 10µA for a normal ramp rate. Between time

points 6 and 7, the ACL ampliﬁer servos the GATE voltage

to track the SS ramp rate, limiting the slew rate of the load

current. At time point 7, SS reaches its ﬁnal value and

GATE continue to ramp up with the 20µA pull-up if the load

current is not in analog current limit. At time point 8, the

FB pin voltage exceeds 0.6V and the second timing cycle

is started. When the conditions of TIMER < 0.2V, ∆VSENSE

< 25mV and ⎯F⎯A⎯U⎯L⎯T high are met, the TIMER capacitor is

allowed to ramp up. When TIMER reaches the VTMR(TH)

threshold at time point 9, ⎯R⎯E⎯S⎯E⎯T goes high, indicating to

the system controller that power is good. After this, the

TIMER is held low.

When the ON pin voltage falls below (VON(TH)–ΔVON(HYST))

threshold (0.72V), it initiates a power-down sequence. At

time point 11, GATE is discharged by both the ACL ampli-

ﬁer and a 100µA current source pull-down, causing the

output voltage to fall gradually. When the FB pin voltage

falls below 0.6V at time point 12, ⎯R⎯E⎯S⎯E⎯T goes low after a

glitch ﬁlter delay (see the section on FB glitch ﬁltering),

indicating that power is bad. When the ON pin voltage falls

below 0.4V, the device resets and GATE is pulled low by a

strong pull-down device.

Soft-Start with Analog Current Limiting

When a very large output load capacitor is connected

during soft-start, the GATE voltage is servoed to regulate

the inrush current to ΔVACL(TH)/RSENSE. This is illustrated

in the timing diagram of Figure 9. After the initial timing

cycle, the GATE is allowed to ramp up, tracking the SS

ramp rate between time points 5 and 8. At time point 7,

when the load current builds up as the GATE pin voltage

increases, the voltage across the sense resistor rises above

ΔVCB(TH) (25mV typical). The FILTER capacitor starts to

charge up by a 60µA current source pull-up. At time point

8, SS reaches its ﬁnal value at the end of SS ramp cycle.

This allows the GATE to be regulated by the ACL ampliﬁer

at ΔVACL(TH) (40mV typical) across the sense resistor,

RSENSE, limiting the inrush to:

LIMIT

SENSE

(9)

The FILTER pin voltage continues to rise as the load ca-

pacitor charges up with the limited load current. At time

point 9, the FB pin voltage exceeds 0.6V, but the second

timing cycle is not allowed to start as the voltage across

the sense resistor exceeds 25mV. At time point 10, the load

current falls as the load capacitor is near full charge and

the voltage across the sense resistor drops below 40mV.

The analog current limit loop shuts off and the GATE ramps

further till its ﬁnal value. The FILTER capacitor discharges

by a 2.4µA pull-down when the voltage across the sense

resistor falls below 25mV at time point 11. The duration

between time points 7 and 11 must be shorter than one

circuit breaker delay, as given by Equation (2), to avoid

a fault time-out during GATE ramp-up for very large load

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