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MSM5259 Datasheet(PDF) 10 Page - OKI electronic componets

No. de pieza MSM5259
Descripción Electrónicos  40-DOT SEGMENT DRIVER
PDF  18 Pages
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Fabricante Electrónico  OKI [OKI electronic componets]
Página de inicio  http://www.oki.com
Logo OKI - OKI electronic componets

MSM5259 Datasheet(HTML) 10 Page - OKI electronic componets

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MSM5259
¡ Semiconductor
10/18
FUNCTIONAL DESCRIPTION
Pin Functional Description
•DI1
The data (1st to 20th bit) from the LCD controller LSI is input to 20-bit shift register from DI1.
(Positive logic)
•DI21
Data input to the shift register (21st to 41st bit).
Connecting DO20 and DI21 allows configuration of a 40-bit register.
If DI21 is not used, connect this pin to VSS.
•CP
Clock pulse input pin for the two 20-bit shift registers. The data is input to the 20-bit shift
register at the falling edge of the clock pulse. A data set up time (tSETUP) and data hold time
(tHOLD) are required between the DI1 and DI21 signals and a clock pulse.
•DO20
20th bit of the shift register contents is output from DO20. The data which was input from DI1
is output from this pin with a delay of the number of bits of the shift register (20), synchronized
with the clock pulse. By connecting DO20 to DI21, two 20-bit shift registers can be used as a
40-bit shift register.
•DO40
40th bit of the shift register contents is output from DO40. The data which was input from DI21
is output from this pin with a delay of the number of bits of the shift register (20), synchronized
with the clock pulse. By connecting DO40 to the next MSM5259’s DI1, this LSI is applicable
to a wide screen LCD.
Refer to the application circuit.
•DF
Alternate signal input pin for LCD driving.
• LOAD
Signal for latching the shift register contents is input from this pin. When the LOAD pin is
set at "H" level, the shift register contents are transferred to the 40-bit 4-level driver. When
LOAD pin is set at "L" level, the last display output data (O1 - O40), which was transferred
when LOAD pin was at "H" level, is held.
•VDD, VSS
Supply voltage pins.
VDD is generally set to 4.0 to 6.0V. VSS is a ground pin (VSS = 0V)
•V2, V3, V5
Bias supply voltage pins to drive the LCD. Bias voltage divided by the register is usually used
as supply voltage source.
Refer to the application circuit.
For static operation, connect V3 to VDD and also connect V2, V5, to VSS.



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