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DA6180B.003

17 September, 2014

MAS6180 PAD LAYOUT

VDD

QOP

QOM

QI

AGC

OUT

DEC

AON

PDN

RFIP

RFIM

VSS

1020 µ

µ

µ

µ

m

VSS pad

bonded first!

MAS6180Bx

DIE size = 1020 µm x 1260 µm; PAD size = 80 µm x 80 µm

Note: Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left

floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly

are recommended to be performed in ESD protected area.

Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.

Pad Identification

Name

X-coordinate

Y-coordinate

Note

Power Supply Voltage

VDD

126 µm

1062 µm

Positive Quartz Filter Output for Crystal

QOP

126 µm

893 µm

Negative Quartz Filter Output for Crystal

QOM

126 µm

723 µm

1

Quartz Filter Input for Crystal and External

Compensation Capacitor

QI

126 µm

549 µm

AGC Capacitor

AGC

126 µm

375 µm

Receiver Output

OUT

126 µm

198 µm

2

Demodulator Capacitor

DEC

894 µm

201 µm

AGC On Control

AON

894 µm

385 µm

3

Power Down

PDN

894 µm

553 µm

4

Positive Receiver Input

RFIP

894 µm

742 µm

5

Negative Receiver Input

RFIM

894 µm

920 µm

5

Power Supply Ground

VSS

894 µm

1051 µm

Notes:

1) External crystal compensation capacitor pin QOM is connected only in MAS6180B5 version. It is left

unconnected in MAS6180B1 version which has internal compensation capacitor.

2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)

-

-

At power down the output is pulled to VSS (pull down switch)

3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (normal operation)

-

Unused AON pad can be left unconnected due to internal pull-up with current < 1 µA. Pull up current is

switched off at power down.

4) PDN = VSS means receiver on; PDN = VDD means receiver off

-

Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up

(PDN=VSS) i.e. at the falling edge of PDN signal.

5) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD