Am79231 Data Sheet
21
Thermal-Management Equations (All Modes except Standby)
TIMING SPECIFICATIONS
Notes:
1. The P1
–3 pins are updated continuously during operation by the LD signal.
2. After a power-on reset or hardware reset, the relay outputs from the Am79231 turn all relays off. An
unassuming state is to place the relay control pins, which are level triggered, to a reset state for all relays.
Any noise encountered only raises the levels toward the register lock state.
3. When writing to the ISLIC registers, the sequence is:
a. Set LD pin to mid-state
b. Place appropriate data on the P1
–3 pins
c. Assert the LD pin to High or Low to write the proper data
d. Return LD pin to mid-state
4. Am79231 registers are refreshed at 5.33 kHz when used with an ISLAC device.
5. If the clock or MPI becomes disabled, the LD pins and P1
–3 returns to 0 V state, thus protecting the Am79231
and the line connection.
6. Not tested in production. Guaranteed by characterization.
R3
A logic 1 on the RD3 signal turns the R3 driver on and routes current from the R3 pin to
the RYE pin. In the option where the RYE pin is connected to ground, the R3 pin can sink
current from a relay connected to VCCD.
Another option is to connect the RYE pin to the B (Ring) lead through a diode and connect
a test load between R3 and the A (Tip) lead. This technique avoids the use of a relay to
connect a test load. However, it does not isolate the subscriber line from the linecard. The
test load must be connected to the Am79231 side of the protection resistor to avoid
damage to the R3 driver.
IL < 5 mA
PSLIC = (SBAT – ILRL) • IL + 0.3 W
PTMG = 0
TMG resistor-current is limited to be 5 mA < IL.
If IL < 5 mA, no current flows in the TMG resistor
and it all flows in the Am79231.
IL > 5 mA
PSLIC = (SBAT – IL(RL + 2 • RFUSE))*IL + 0.3 W – PTMG
PTMG = (IL – 5 mA)^2 • (RTMG1 + RTMG2)
These equations are valid when
RTMGX • (IL – 5mA) < (SBAT – RLIL)/2 – 2
because the longitudinal voltage is one-half the
battery voltage and the TMG switches require
approximately 2 V.
Symbol
Signal
Parameter
Min
Typ
Max
Unit
trSLD
LD
Rise time Am79231 LD pin
2
µs
tfSLD
LD
Fall time Am79231 LD pin
2
tSLDPW
LD
LD minimum pulse width
3
tSDXSU
P1,P2,P3
P1–3 data Setup time
4.5
tSDXHD
P1,P2,P3
P1–3 data hold time
4.5
tSDXD
P1,P2,P3
Max P1–3 data delay
5
Driver
Description
Mexican ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
