CD4070B datasheet(4/5 Pages) SS

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CMOS High Voltage Logic – CD4070B

Rev 1.0

15/03/18

LIMITS

PARAMETER

SYMBOL

VDD

CONDITIONS

25°C

85°C

FULL RANGE

UNITS

280

560

10V

130

260

Maximum

Propagation Delay,

Input to Output

(Figure 1)

tPLH, tPHL

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

100

200

400

10V

100

200

Maximum Output

Transition Time, Any

Output (Figure 1)

tTLH, tTHL

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

160

TYPICAL

Maximum Input

Capacitance

CIN

TA = 25°C

VIN = 0V

AC Electrical Characteristics5

5. Not production tested in die form, characterized by chip design and tested in package.

Switching Waveform

Figure 1 – Propagation Delay, Output Timing

LIMITS

PARAMETER

SYMBOL

VDD

CONDITIONS

25°C

85°C

FULL RANGE

UNITS

VOL = 0.4V

0.64

0.51

0.36

10V

VOL = 0.5V

1.6

1.3

0.9

Minimum Output

(Sink) Current

IOL

15V

VOL = 1.5V

4.2

3.4

2.4

Maximum Input

Leakage Current

IIN

15V

VIN = VDD or VSS

±0.1

±1.0

µA

0.25

7.5

10V

0.5

Maximum Quiescent

Current

IDD

15V

VIN = VDD or VSS

1.0

µA

DC Electrical Characteristics (Voltages referenced to V

SS)

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