High Speed CMOS Logic – 54HC08

 

Rev 1.0

07/02/19

 

LIMITS

PARAMETER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5. Not production tested in die form, characterized by chip design and tested in package.

SYMBOL

CONDITIONS

FULL RANGE

4

UNITS

25°C

85°C

2.0V

1.9

1.9

1.9

4.5V

4.4

4.4

4.4

6.0V

5.9

5.9

5.9

V

3.0V

2.48

2.34

2.20

4.5V

3.98

3.84

3.70

Minimum High-Level

Output Voltage

6.0V

5.48

5.34

5.20

V

2.0V

0.1

0.1

0.1

4.5V

0.1

0.1

0.1

6.0V

0.1

0.1

0.1

V

3.0V

0.26

0.33

0.40

4.5V

0.26

0.33

0.40

Maximum Low-Level

Output Voltage

6.0V

0.26

0.33

0.40

V

Maximum Input

Leakage Current

6.0V

±0.1

±1.0

±1.0

µA

Maximum Quiescent

Supply Leakage

Current

6.0V

1

10

40

µA

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0V

75

95

110

3.0V

30

40

55

4.5V

15

19

22

Maximum Propagation

Delay, Input A or B to

Output Y

(Figure 1,2)

6.0V

Input

13

16

19

ns

2.0V

75

95

110

3.0V

27

32

36

4.5V

15

19

22

Maximum Output Rise

and Fall Time,

Any Output

(Figure 1,2)

Input

ns

6.0V

13

16

19

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