MP7652

10

Rev. 1.00

Figure 7. 8085 Interface (Simplified Diagram)

ALE

WR

SOD

8085

8

8

DATA BUS

+5

8212

A0 to A2

ADDRESS

DECODER

74LS138

E1

E3

E2

SDI

CLK

LD

PRESET

FROM SYSTEM RESET

8

ADDRESS BUS

NOTES:

1.

Clock generated by WR and decoding address 8000

2.

Data is clocked into the DAC shift register by executing memory write instructions. the clock input is

generated by decoding address 8000 and WR. Data is then loaded into the DAC register with a memory

write instruction to address 4000.

3.

Serial data must be present in the right justified format in registers H & L of the microprocessor.

3

MP7652