AM79C987 datasheet(7/30 Pages) AMD

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AMD

P R E L I M I N A R Y

Am79C987

FUNCTIONAL DESCRIPTION

Overview

The functional specification of the HIMIB device is a su-

perset of that defined by the Layer Management for

10 Mbyte/s

Baseband

Repeaters

Standard

(IEEE802.3k), commonly referred to as the “Repeater

Management Standard.” The HIMIB chip contains the

complete set of repeater and port functions as defined in

the standard. All mandatory and optional capabilities

are supported. These are defined as the Basic Control,

Performance Monitor and Address Tracking Capabili-

ties. In addition, node address mapping and MAU man-

agement specific functions are implemented.

The HIMIB device keeps track of the IEEE 802.3k speci-

fied attributes by extracting data from the expansion

port, management port, and port activity monitor (PAM)

port of the IMR+ device. All attribute counts are held in

32 bit registers, as specified in the Repeater Manage-

ment Standard. For more detailed information, refer to

the IEEE 802.3 Layer Management for 10 Mbyte/s

Baseband Repeaters Standard and AMD’s IEEE 802.3

Repeater Technical Manual (PID #17314A).

The HIMIB chip supports the following Repeater Man-

agement functions:

Repeater Attributes:

Transmit Collisions – 32-bit counter

Total Octets – 32-bit counter

Port Attributes:

Auto Partition State – from IMR+ chip

Readable Frames – 32-bit counter

Readable Octets – 32-bit counter

Frame Check Sequence Errors – 32-bit counter

Alignment Errors – 32-bit counter

Frames Too Long – 32-bit counter

Short Events – 32-bit counter

Runts – 32-bit counter

Collisions – 32-bit counter

Late Events – 32-bit counter

Very Long Events – 32-bit counter

Data Rate Mismatches – 32-bit counter

Auto Partitions – 32-bit counter

Source Address Changes – 32-bit counter

Last Source Address – 48-bit register

Node ID to Port Address Map:

Source Address Match Register (48-bit register)

Port Actions:

Port Admin Control (Enable / Disable).

Note: The HIMIB device executes this action by direct

access to the IMR+ device Management Port.

Individually maskable Interrupts are available for the fol-

lowing events:

Change in the Port Partitioning Status

Change in the Twisted Pair Ports Link Test State

AUI Loop Back Error

AUI SQE Test Error

Source Address Changed

Source Address Match

IMR+ Interface Error

The HIMIB chip provides direct access to the manage-

ment port of the IMR+ device for additional functions in-

cluding twisted pair port automatic receive polarity

detection/correction state and enabling the alternate re-

connection algorithm.

The HIMIB device’s 8-bit microprocessor interface al-

lows access to onboard registers. The interface is de-

signed to be usable with a variety of available

microprocessors and buses.

The HIMIB device can also be used to collect network

statistics from a standard 802.3 MAC device. This mode

is programmed by setting the MAC Interface Mode En-

able bit in the Configuration Register. In this mode the

HIMIB device can be interfaced with any Ethernet con-

troller with a general purpose serial interface (GPSI).

The HIMIB device will record various network events oc-

curring at that node of the network, and assign these

gathered statistics to the AUI port. All TP ports statistics

are invalid in this mode.

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