AM79C987JC datasheet(14/30 Pages) AMD

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P R E L I M I N A R Y

Am79C987

If a Get command is written to this register accidentally,

the IMR+ device output will be retained in the Get regis-

ter, however, the management Interface Error bit will be

set in the Status Register. Writing to this register prior to

execution (transfer) of the last command (Get or Set)

causes the processor to be placed into the wait state.

IMR+ Management Port Get Register (G)

P[4:0] = 0, R[4:0] = 31

D Port Read/Write

MSB

LSB

This is a read/write register. This register is used to

transfer a Get command to the IMR+ device. This is per-

formed by serializing and transferring the command

placed into this register to the IMR+ device following the

end of the processor write cycle that writes the Get com-

mand. The byte returned by the IMR+ chip is then

placed in this register, overwriting its previous content.

The microprocessor can read the byte result of the Get

operation once the information has been transferred to

the HIMIB device. If the read operation is started prior to

completion of this transfer the HIMIB device will hold the

RDY line inactive until the transfer is complete. In most

applications this will insert wait states into the processor

read cycle.

If a Set command is written to this register accidentally,

the IMR+ device will receive the Set command. How-

ever, the management Interface Error bit will be set in

the Status Register.

Note that reading the IMR+ Twisted Pair Bit Rate Error

Status Registers using the Get command may affect ac-

curacy of the Bit Rate Error attribute.

Port Status Registers

These registers are accessed by writing the bit pattern

0000 0001 to the C port, i.e., P[4:0] = 1. These registers

are read only and are cleared to 0 upon reading.

TP and AUI Partition Status Change

Any port changing state from the partitioned to the re-

connected state, or vice versa, causes the appropriate

bit to be set to 1, in one of these two registers.

TP Ports

P[4:0] = 1, R[4:0] = 0

The format for the TP ports is:

D Port Read

MSB

LSB

AUI Port

P[4:0] = 1, R[4:0] = 1

For the AUI port, only the most significant bit is used.

Bits denoted as X are undefined.

D Port Read

MSB

LSB

TP Link Status Change

P[4:0] = 1, R[4:0] = 2

A change in the Link Test state of a TP port (from Link

Fail to Link Pass or vice versa), causes the appropriate

bit to be set to 1 in this register:

D Port Read

MSB

LSB

AUI Loop Back Error

P[4:0] = 1, R[4:0] = 3

This register is not valid for the IMR device

(Am79C980). When the HIMIB chip is interfaced with

the IMR+ device (Am79C981), the most significant bit

(A) is set to 1 if the AUI port is connected to a MAU which

does not loopback data from DO to DI during transmis-

sion. For the error to be detected, the network needs to

be active and a packet transmitted from the AUI port.

Bits denoted as X are undefined.

D Port Read

MSB

LSB

Note that if the DO to DI loopback path is not opera-

tional, this bit will be set again when the next packet is

transmitted via the AUI port.

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