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GD25Q256DFER Datasheet(PDF) 81 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25Q256DFER Datasheet(HTML) 81 Page - GigaDevice Semiconductor (Beijing) Inc. |
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81 / 89 page ![]() 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 81 tBP1 Byte Program Time (First Byte) 30 60 μs tBP2 Additional Byte Program Time (After First Byte) 2.5 15 μs tPP Page Programming Time 0.4 2.5 ms tSE Sector Erase Time 70 450 ms tBE1 Block Erase Time (32K Bytes) 0.16 1.2 s tBE2 Block Erase Time (64K Bytes) 0.22 2 s tCE Chip Erase Time (GD25Q256D) 70 260 s Note: 1. Typical value tested at T = 25℃. 2. Value guaranteed by design and/or characterization, not 100% tested in production. Figure 78. Serial Input Timing Figure 79. Output Timing Figure 80. Resume to Suspend Timing CS# Resume Command tRS Suspend Command SCLK CS# SI MSB SO High-Z LSB tCHSL tSLCH tDVCH tCHDX tSHCH tCHSH tCHCL tCLCH tSHSL CS# SCLK SO SI Least significant address bit (LIB) in tCLQV tCLQX tCLQX tCLQV tCLH tCLL tSHQZ LSB |
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