Data Sheet

ADRF5721

Rev. 0 | Page 7 of 17

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

D4/SERIN

Parallel Control Input for 8 dB Attenuator Bit (D4).

Serial Data Input (SERIN). See the Theory of Operation section for more information.

2

D5/CLK

Parallel Control Input for 16 dB Attenuator Bit (D5).

Serial Clock Input (CLK). See the Theory of Operation section for more information.

3, 5 to 8, 10

GND

Ground. These pins must be connected to the RF and dc ground of the PCB.

4

ATTIN

Attenuator Input. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is needed

when the RF line potential is equal to 0 V dc.

9

ATTOUT

Attenuator Output. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is

needed when the RF line potential is equal to 0 V dc.

11

VSS

Negative Supply Input.

12

VDD

Positive Supply Input.

13

LE

Latch Enable Input. See the Theory of Operation section for more information.

14

PS

Parallel or Serial Control Interface Selection Input. See the Theory of Operation section for more

information.

15

D2

Parallel Control Input for 2 dB Attenuator Bit. See the Theory of Operation section for more information.

16

D3/SEROUT

Parallel Control Input for 4 dB Attenuator Bit (D3).

Serial Data Output (SEROUT). See the Theory of Operation section for more information.

17

EPAD

Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB.

INTERFACE SCHEMATICS

Figure 5. Digital Input Interface Schematic for LE, PS, D3/SEROUT, D4/SERIN,

and D5/CLK

Figure 6. ATTIN and ATTOUT Interface Schematic

Figure 7. Digital Input Interface Schematic for D2

VDD

D4/SERIN

VSS

GND

ATTOUT

D5/CLK

GND

ATTIN

ADRF5721

TOP VIEW

(Not to Scale)

NOTES

1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED

TO THE RF AND DC GROUND OF THE PCB.

1

2

3

4

12

11

10

9

6

5

7

8

16

15

14

13

VDD

VDD

LE, PS, D3/SEROUT,

D4/SERIN, D5/CLK

ATTIN,

ATTOUT

VDD

VDD

100kΩ

D2