STR720 datasheet(253/401 Pages) STMICROELECTRONICS

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STR720 - CONTROLLER AREA NETWORK (CAN)

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When the phase error of the edge which causes Re-synchronization is positive,

Phase_Seg1 is lengthened. If the magnitude of the phase error is less than SJW,

Phase_Seg1 is lengthened by the magnitude of the phase error, else it is lengthened by

SJW.

When the phase error of the edge, which causes Re-synchronization is negative,

Phase_Seg2 is shortened. If the magnitude of the phase error is less than SJW,

Phase_Seg2 is shortened by the magnitude of the phase error, else it is shortened by

SJW.

When the magnitude of the phase error of the edge is less than or equal to the programmed

value of SJW, the results of Hard Synchronization and Re-synchronization are the same. If the

magnitude of the phase error is larger than SJW, the Re-synchronization cannot compensate

the phase error completely, an error (phase error - SJW) remains.

Only one synchronization may be done between two Sample Points. The Synchronizations

maintain a minimum distance between edges and Sample Points, giving the bus level time to

stabilize and filtering out spikes that are shorter than (Prop_Seg + Phase_Seg1).

Apart from noise spikes, most synchronizations are caused by arbitration. All nodes

synchronize “hard” on the edge transmitted by the “leading” transceiver that started

transmitting first, but due to propagation delay times, they cannot become ideally

synchronized. The “leading” transmitter does not necessarily win the arbitration, therefore the

receivers have to synchronize themselves to different transmitters that subsequently “take the

lead” and that are differently synchronized to the previously “leading” transmitter. The same

happens at the acknowledge field, where the transmitter and some of the receivers will have

to synchronize to that receiver that “takes the lead” in the transmission of the dominant

acknowledge bit.

Synchronizations after the end of the arbitration will be caused by oscillator tolerance, when

the differences in the oscillator’s clock periods of transmitter and receivers sum up during the

time between synchronizations (at most ten bits). These summarized differences may not be

longer than the SJW, limiting the oscillator’s tolerance range.

The examples in Figure 37 show how the Phase Buffer Segments are used to compensate for

phase errors. There are three drawings of each two consecutive bit timings. The upper

drawing shows the synchronization on a “late” edge, the lower drawing shows the

synchronization on an “early” edge, and the middle drawing is the reference without

synchronization.

STR720 Datasheet(PDF) 253 Page - STMicroelectronics