STR720 datasheet(257/401 Pages) STMICROELECTRONICS

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STR720 - CONTROLLER AREA NETWORK (CAN)

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18.7.10.5 Configuring the CAN Protocol Controller

In most CAN implementations and also in the CAN Peripheral, the bit timing configuration is

programmed in two register bytes. The sum of Prop_Seg and Phase_Seg1 (as TSEG1) is

combined with Phase_Seg2 (as TSEG2) in one byte, SJW and BRP are combined in the

other byte (see Figure 39 on page 257).

In these bit timing registers, the four components TSEG1, TSEG2, SJW, and BRP have to be

programmed to a numerical value that is one less than its functional value. Therefore, instead

of values in the range of [1..n], values in the range of [0..n-1] are programmed. That way, e.g.

SJW (functional range of [1..4]) is represented by only two bits.

Therefore the length of the bit time is (programmed values) [TSEG1 + TSEG2 + 3] tq or

(functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq.

The data in the bit timing registers is the configuration input of the CAN protocol controller.

The Baud Rate Prescaler (configured by BRP) defines the length of the time quantum, the

basic time unit of the bit time; the Bit Timing Logic (configured by TSEG1, TSEG2, and SJW)

defines the number of time quanta in the bit time.

The processing of the bit time, the calculation of the position of the Sample Point, and

occasional synchronizations are controlled by the BTL state machine, which is evaluated once

Figure 39. Structure of the CAN Core’s CAN Protocol Controller

Sample_Point

Bit_to_send

Sync_Mode

Bus_Off

Scaled_Clock (tq)

System Clock

Receive_Data

Transmit_Data

Control

Received_Message

Send_Message

Status

Bit

Timing

Logic

Baudrate_

Prescaler

Sampled_Bit

Configuration (TSEG1, TSEG2, SJW)

Configuration (BRP)

Shift-Register

Received_Data_Bit

Next_Data_Bit

Control

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