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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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STR720 Datasheet(PDF) 312 Page - STMicroelectronics |
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STR720 Datasheet(HTML) 312 Page - STMicroelectronics |
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312 / 401 page  STR720 - EXTENDED FUNCTION TIMER (EFT) 312/401 21.3.2 External Clock The external clock (where available) is selected if ECKEN = 1 in CR1 register. The status of the EXEDG bit determines the type of level transition on the external clock pin EXTCLK that will trigger the counter. The counter is synchronized with the rising edge of the internal clock coming from the APB block. At least four rising edges of the APB_CLK must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the APB clock frequency. Figure 44. Counter Timing Diagram, internal clock divided by 2 Figure 45. Counter Timing Diagram, internal clock divided by 4 APB_CLK FFFD FFFE FFFF 0000 0001 0002 0003 INTERNAL RESET TIMER STROBE: COUNTER REGISTER OVERFLOW FLAG TOF FFFC FFFD 0000 0001 APB_CLK INTERNAL RESET TIMER STROBE COUNTER REGISTER OVERFLOW FLAG TOF 1 |
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