STR720 datasheet(360/401 Pages) STMICROELECTRONICS

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STR720 - MISCELLANEA REGISTERS (GCR - CGC - AHB_ERR)

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24.5 AHB Error detection block description

Due to the specific implementation of ARM720T AHB interface, any AHB transfer resulting in

an error response from the addressed slave, is not detected directly by the core. Detecting

these events is particularly helpful during application software debug, when due to an

incorrect configuration some inconsistent memory access can be attempted. In order to

detected these events a specific block is implemented, which monitors AHB activity and

generates a FIQ request to the core, storing the value of the address which caused the error

response to be triggered. Here are the few registers by which this block operation can be

configured and used.

AHB Error Pending (AERR_P)

Address: 0xF000_3000

Reset value: 0x0000_0000

This register stores the pending bit which is set by hardware at the occurrence of an AHB

error. The register is read-clear in the sense that application software can only write ‘0’ into

this bit, to acknowledge the detected error and re-enable AHB bus monitoring. Writing ‘1’ into

this register has no effect.

Bits 31:1 = Reserved. These bits must be always written to 0.

Bit 0 = AE_P: AHB Error Pending

0: No AHB error detected.

1: An AHB transfer resulted into an error response.

Reserved

765432

Reserved

AE_P

-rc

STR720 Datasheet(PDF) 360 Page - STMicroelectronics